Address-remapped memory chip, memory module and memory system including the same
    2.
    发明授权
    Address-remapped memory chip, memory module and memory system including the same 有权
    地址重映射存储芯片,内存模块和内存系统包括相同

    公开(公告)号:US09570132B2

    公开(公告)日:2017-02-14

    申请号:US14803119

    申请日:2015-07-20

    Abstract: A memory chip includes a chip input-output pad unit, a plurality of semiconductor dies. The chip input-output pad unit includes a plurality of input-output pins connected to an external device and the plurality of semiconductor dies are connected commonly to the chip input-output pad unit and having a full memory capacity respectively. Each semiconductor die includes a die input-output pad unit, a memory region and a conversion block. The die input-output pad unit includes a plurality of input-output terminals respectively connected to the input-output pins of the chip input-output pad unit. The memory region includes an activated region corresponding to a portion of the full memory capacity and a deactivated region corresponding to a remainder portion of the full memory capacity. The conversion block connects the activated region except the deactivated region to the die input-output pad unit.

    Abstract translation: 存储器芯片包括芯片输入 - 输出焊盘单元,多个半导体管芯。 芯片输入输出焊盘单元包括连接到外部设备的多个输入输出引脚,并且多个半导体管芯分别连接到芯片输入 - 输出焊盘单元并具有完全存储器容量。 每个半导体管芯包括管芯输入 - 输出焊盘单元,存储区域和转换块。 管芯输入 - 输出焊盘单元包括分别连接到芯片输入 - 输出焊盘单元的输入 - 输出引脚的多个输入 - 输出端子。 存储器区域包括对应于全部存储器容量的一部分的激活区域和对应于完整存储器容量的剩余部分的去激活区域。 转换块将去激活区域之外的激活区域连接到管芯输入 - 输出焊盘单元。

    MEMORY DEVICE THAT PERFORMS INTERNAL COPY OPERATION

    公开(公告)号:US20190079760A1

    公开(公告)日:2019-03-14

    申请号:US16189642

    申请日:2018-11-13

    Abstract: A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

    Memory device that performs internal copy operation

    公开(公告)号:US10983792B2

    公开(公告)日:2021-04-20

    申请号:US16189642

    申请日:2018-11-13

    Abstract: A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

    Memory device
    6.
    发明授权

    公开(公告)号:US09412470B2

    公开(公告)日:2016-08-09

    申请号:US14590717

    申请日:2015-01-06

    Abstract: A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal.

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