公开(公告)号：US20230170290A1

公开(公告)日：2023-06-01

申请号：US17886872

申请日：2022-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： YUN-HEE LEE ,  JAESUN KIM ,  SEOKBEOM YONG ,  WONJAE LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/2919 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2924/0665

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate and a semiconductor chip on the redistribution substrate. The redistribution substrate includes a plurality of first conductive patterns including a pair of first signal patterns that are adjacent to each other, and a plurality of second conductive patterns on surfaces of the first conductive patterns and coupled to the first conductive patterns. The second conductive patterns include a ground pattern insulated from the pair of first signal patterns. The ground pattern has an opening that penetrates the ground pattern. When viewed in plan, the pair of first signal patterns overlap the opening.

公开(公告)号：US20250167155A1

公开(公告)日：2025-05-22

申请号：US18785840

申请日：2024-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGSOO HA ,  Seunggeol RYU ,  YUN-HEE LEE ,  Yiseul HAN

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/49 ,  H01L23/498 ,  H01L25/10 ,  H10B80/00

Abstract: A semiconductor package may include a lower redistribution layer, a first semiconductor chip on the lower redistribution layer, a second semiconductor chip on the first semiconductor chip, under-bump patterns between the first semiconductor chip and the second semiconductor chip, and connection terminals between the under-bump patterns and the second semiconductor chip. The under-bump patterns may include a first under-bump pattern connected to two of the connection terminals and a second under-bump pattern connected to one of the connection terminals. A power or ground voltage of the second semiconductor chip may be applied through the first under-bump pattern.

公开(公告)号：US20190385997A1

公开(公告)日：2019-12-19

申请号：US16554818

申请日：2019-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-YOUN CHOI ,  EUN-SEOK SONG ,  SEUNG-YONG CHA ,  YUN-HEE LEE

IPC: H01L25/18 ,  H01L23/538 ,  H01F27/28 ,  H01F27/24 ,  H01L25/065

Abstract: An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.

公开(公告)号：US20180190635A1

公开(公告)日：2018-07-05

申请号：US15696973

申请日：2017-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-YOUN CHOI ,  EUN-SEOK SONG ,  SEUNG-YONG CHA ,  YUN-HEE LEE

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01F27/28 ,  H01F27/24

Abstract: An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.