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    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20250028456A1

    公开(公告)日：2025-01-23

    申请号：US18907760

    申请日：2024-10-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungho Lee ,  Kiheung Kim ,  Taeyoung Oh ,  Jongcheol Kim ,  Hyongryol Hwang

    IPC: G06F3/06

    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows and a row hammer management circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row. The row hammer management circuit includes a hammer address queue. The row hammer management circuit changes the updated count data randomly, based on an event signal indicating a state change of the hammer address queue.

    Semiconductor memory devices and memory systems including the same
    3.
    发明授权
    Semiconductor memory devices and memory systems including the same 有权

    公开(公告)号：US12118221B2

    公开(公告)日：2024-10-15

    申请号：US18136915

    申请日：2023-04-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongcheol Kim ,  Kiheung Kim ,  Taeyoung Oh ,  Kyungho Lee

    IPC: G06F12/00 ,  G06F3/06

    CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A semiconductor memory device includes a memory cell array, a row hammer management circuit and a refresh control circuit. The row hammer management circuit automatically stores random count data in count cells of each of a plurality of memory cell rows during a power-up sequence of the semiconductor memory device and determines counted values by counting a number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller and stores the counted values in the count cells of each of the plurality of memory cell rows as count data. The refresh control circuit receives a hammer address and performs a hammer refresh operation on one or more of the plurality of memory cell rows that are physically adjacent to a memory cell row that corresponds to the hammer address.

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240220149A1

    公开(公告)日：2024-07-04

    申请号：US18243268

    申请日：2023-09-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Taeyoung Oh

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0673

    Abstract: A semiconductor memory device includes a memory cell array and a column access circuit. The memory cell array includes a plurality of sub-array blocks and each of the sub-array blocks includes volatile memory cells. The column access circuit receives a plurality of data units, each of which includes normal data and meta data having a ratio of k:1, which is associated with managing the normal data, allocates p column selection lines associated with transferring the data units to the bit-lines to a plurality of normal data and a plurality of meta data in the data units with the ratio of k:1, and stores a sub unit of a first normal data among the plurality of normal data and a sub unit of a first meta data in a first region and a second region of a first sub-array block of the plurality of sub-array blocks, respectively.

    SEMICONDUCTOR MEMORY DEVICE AND METHODS OF OPERATION
    6.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND METHODS OF OPERATION 审中-公开

    公开(公告)号：US20230185460A1

    公开(公告)日：2023-06-15

    申请号：US18076628

    申请日：2022-12-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Taeyoung Oh ,  Hyeran Kim ,  Sungyong Cho ,  Kyungsoo Ha

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673

    Abstract: A semiconductor memory device includes a memory cell array, a row hammer management circuit and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The row hammer management circuit counts the number of instances of access of each of the memory cell rows, such as in response to the receipt of an active command, to store the counted values in count cells of each of the memory cell rows as count data and, in response to a first command, initiates an internal read-update-write operation to read the count data, to update the read count data, and to write the updated count data in the count cells. The control logic circuit may performs an internal write operation to write the updated count data in the count cells during a second write time interval that is smaller than a first write time interval associated with a normal write operation.

    Semiconductor memory including pads arranged in parallel
    7.
    发明授权
    Semiconductor memory including pads arranged in parallel 有权

    公开(公告)号：US10665558B2

    公开(公告)日：2020-05-26

    申请号：US16036198

    申请日：2018-07-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sihong Kim ,  Young-Hoon Son ,  Taeyoung Oh ,  Kyung-Soo Ha

    IPC: H01L23/00 ,  G11C5/06 ,  G11C8/10 ,  G11C5/04 ,  G11C5/02

    Abstract: A semiconductor memory includes a plurality of first pads arranged in a first direction, a plurality of second pads arranged parallel to the plurality of first pads and in the first direction, a plurality of third pads arranged in a second direction perpendicular to the first direction, and a plurality of fourth pads arranged in the second direction. The semiconductor memory further includes first interconnection wires extending from the plurality of first pads in the second direction, the first interconnection wires being connected to the plurality of third pads, and second interconnection wires extending from the plurality of second pads in an opposite direction to the second direction, the second interconnection wires being connected to the plurality of fourth pads.

    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20240411467A1

    公开(公告)日：2024-12-12

    申请号：US18811955

    申请日：2024-08-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongcheol Kim ,  Kiheung Kim ,  Taeyoung Oh ,  Kyungho Lee

    IPC: G06F3/06

    Abstract: A semiconductor memory device includes a memory cell array, a row hammer management circuit and a refresh control circuit. The row hammer management circuit automatically stores random count data in count cells of each of a plurality of memory cell rows during a power-up sequence of the semiconductor memory device and determines counted values by counting a number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller and stores the counted values in the count cells of each of the plurality of memory cell rows as count data. The refresh control circuit receives a hammer address and performs a hammer refresh operation on one or more of the plurality of memory cell rows that are physically adjacent to a memory cell row that corresponds to the hammer address.

    SEMICONDUCTOR MEMORY DEVICES
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20240371417A1

    公开(公告)日：2024-11-07

    申请号：US18771859

    申请日：2024-07-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongcheol Kim ,  Hyunsung Shin ,  Hohyun Shin ,  Taeyoung Oh ,  Kyungsoo Ha

    IPC: G11C7/10 ,  G06F3/06 ,  G06F11/10 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096

    Abstract: A semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gating circuit and a control logic circuit. The memory cell array includes a plurality of sub array blocks arranged in a first direction and a second direction. The data VO buffer exchanges user data with a memory controller through I/O pads. The I/O gating circuit is connected to the data I/O buffer through data buses and connected to the memory cell array through data I/O lines, and programs mapping relationship between the sub array blocks and the I/O pads, based on a mapping control signal such that uncorrectable errors that are detected by an error correction code engine in the memory controller are reduced. The control logic circuit generates the mapping control signal based on identifier information indicating a type of a central processing unit of the memory controller.

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