公开(公告)号：US10651179B2

公开(公告)日：2020-05-12

申请号：US15992623

申请日：2018-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-bae Park ,  Ja-hum Ku ,  Myeong-cheol Kim ,  Jin-wook Lee ,  Sung-kee Han

IPC: H01L27/11 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L21/02 ,  H01L23/528 ,  H01L29/06 ,  H01L29/66

Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

公开(公告)号：US10014304B2

公开(公告)日：2018-07-03

申请号：US15333491

申请日：2016-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-bae Park ,  Ja-hum Ku ,  Myeong-cheol Kim ,  Jin-wook Lee ,  Sung-kee Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238 ,  H01L21/02 ,  H01L23/528

CPC classification number: H01L27/1104 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.