公开(公告)号：US09490130B2

公开(公告)日：2016-11-08

申请号：US14726648

申请日：2015-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong In Yun ,  Jin-Soo Lim ,  Hansoo Kim ,  Sung-Hwan Jang ,  Youngwoo Park ,  Byoungkeun Son

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/28 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L21/311

CPC classification number: H01L29/78 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A method of manufacturing a three-dimensional semiconductor memory device comprises forming a thin layer structure by alternately stacking first and second material layers on a substrate, forming a penetration dent penetrating the thin layer structure and exposing a top surface of the substrate recessed by the penetration dent, forming a vertical insulation layer penetrating the thin layer structure to cover an inner wall of the penetration dent, forming a semiconductor pattern penetrating the vertical insulation layer at the penetration dent to be inserted into the substrate, and forming an oxide layer between the thin layer structure and the substrate by oxidizing a sidewall of the penetration dent.

Abstract translation: 一种制造三维半导体存储器件的方法包括通过在衬底上交替地堆叠第一和第二材料层来形成薄层结构，形成穿透薄层结构的穿透凹陷，并使基底凹陷的顶部表面露出 形成穿透薄层结构的垂直绝缘层以覆盖穿透凹陷的内壁，形成穿透穿孔凹陷处的垂直绝缘层的半导体图案，以插入到基板中，并且在薄的层间形成氧化物层 通过氧化渗透凹陷的侧壁来形成层状结构和基底。

公开(公告)号：US10521959B2

公开(公告)日：2019-12-31

申请号：US15687605

申请日：2017-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Hyun Lee ,  Sung-Hwan Jang ,  Sung-Youn Chung ,  Jae-Hoon Jeong

IPC: G06F17/30 ,  G06T17/20 ,  G06K9/62 ,  G06K9/00 ,  G06K9/40 ,  G06T19/20

Abstract: To reduce structure noise, input data representing an input structure is obtained and boundary conditions are set by classifying data of each of multiple structure elements of the input data as a signal component or a noise component. A smoothing operation is performed with respect to the input data and based on the boundary conditions. Output data representing an output structure is provided by reducing noise from the input structure.

公开(公告)号：US10068038B2

公开(公告)日：2018-09-04

申请号：US15277480

申请日：2016-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Hwan Jang ,  Sungchul Kim ,  Jiseong Doh ,  Wonsok Lee

IPC: G06F17/50

Abstract: A semiconductor process simulation method includes classifying a semiconductor process simulation into a plurality of blocks based on an annealing simulation, performing a shape simulation corresponding to a block selected from the plurality of blocks, and performing at least two ion implantation simulations among a plurality of ion implantation simulations corresponding to the selected block in parallel, based on result data of the shape simulation corresponding to the selected block.

公开(公告)号：US20250056789A1

公开(公告)日：2025-02-13

申请号：US18620333

申请日：2024-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Jin Nam ,  Sung-Hwan Jang ,  Won Hee Choi ,  Sung Uk Jang

IPC: H10B12/00

Abstract: The present disclosure relates to semiconductor memory devices. An example semiconductor memory device comprises a substrate, a structure including word lines and interlayer insulating films alternately stacked on the substrate, a channel region disposed between two adjacent word lines in a vertical direction, a first source/drain region disposed on a first side of the channel region, a second source/drain region disposed on a second side of the channel region, a bit line which extends in the vertical direction on the substrate and is connected to the first source/drain region, a capping insulating film disposed between the bit line and the word lines, and a data storage connected to the second source/drain region. At least a part of the first source/drain region protrudes from a sidewall of the capping insulating film toward the bit line.

公开(公告)号：US11495284B2

公开(公告)日：2022-11-08

申请号：US17202466

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Ho Moon ,  Sung-Hwan Jang

IPC: G11C7/12 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/4076

Abstract: Disclosed are a memory device and an operating method thereof. The memory device includes a bitline sense amplifier connected to a bitline and a complementary bitline connected to a memory cell, and a sense amplifier driver circuit. The bitline sense amplifier senses and amplifies a voltage difference by developing a voltage of the bitline and a voltage of the complementary bitline. The sense amplifier driver circuit includes a pull-up circuit adjusting a level of a bitline low-level voltage developed by the bitline sense amplifier to be higher than a ground voltage in response to a first pull-up pulse, and a pull-down circuit adjusting the level of the bitline low level adjusted by the pull-up circuit to be equal to the ground voltage in response to a pull-down pulse. A pulse generator generates the first pull-up pulse and the pull-down pulse based on a command received from a host.