公开(公告)号：US10325898B2

公开(公告)日：2019-06-18

申请号：US15635615

申请日：2017-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sharma Deepak ,  Rajeev Ranjan ,  Kuchanuri Subhash ,  Chulhong Park ,  Jaeseok Yang ,  Kwanyoung Chun

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/092

Abstract: A semiconductor device includes a first active pattern extending in a first direction on a first region and a second region of a substrate, a first dummy gate electrode extending in a second direction crossing the first active pattern between the first region and the second region, a contact structure contacting the first dummy gate electrode and extending in the first direction, and a power line disposed on the contact structure and electrically connected to the contact structure. The power line extends in the first direction. The contact structure overlaps with the power line when viewed in a plan view.

公开(公告)号：US20180158811A1

公开(公告)日：2018-06-07

申请号：US15655125

申请日：2017-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kuchanuri Subhash ,  Rastogi Sidharth ,  Deepak Sharma ,  Chul-hong Park ,  Jae-seok Yang

IPC: H01L27/02 ,  H01L23/528 ,  H01L27/118 ,  H01L27/11 ,  H01L27/105

CPC classification number: H01L27/0207 ,  H01L23/5283 ,  H01L27/105 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11883 ,  H03K19/00

Abstract: An integrated circuit (IC) device includes at least one standard cell. The at least one standard cell includes: first and second active regions respectively disposed on each of two sides of a dummy region, the first and second active regions having different conductivity types and extending in a first direction; first and second gate lines extending parallel to each other in a second direction perpendicular to the first direction across the first and second active regions, a first detour interconnection structure configured to electrically connect the first gate line with the second gate line; and a second detour interconnection structure configured to electrically connect the second gate line with the first gate line. The first and second detour interconnection structures include a lower interconnection layer extending in the first direction, an upper interconnection layer extending in the second direction, and a contact via.

公开(公告)号：US10249605B2

公开(公告)日：2019-04-02

申请号：US15655125

申请日：2017-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kuchanuri Subhash ,  Rastogi Sidharth ,  Deepak Sharma ,  Chul-hong Park ,  Jae-seok Yang

IPC: H01L27/02 ,  H01L23/528 ,  H01L27/118 ,  H01L27/11 ,  H01L27/105 ,  H03K19/00

Abstract: An integrated circuit (IC) device includes at least one standard cell. The at least one standard cell includes: first and second active regions respectively disposed on each of two sides of a dummy region, the first and second active regions having different conductivity types and extending in a first direction; first and second gate lines extending parallel to each other in a second direction perpendicular to the first direction across the first and second active regions, a first detour interconnection structure configured to electrically connect the first gate line with the second gate line; and a second detour interconnection structure configured to electrically connect the second gate line with the first gate line. The first and second detour interconnection structures include a lower interconnection layer extending in the first direction, an upper interconnection layer extending in the second direction, and a contact via.