SEMICONDUCTOR PACKAGE
    2.
    发明申请

    公开(公告)号:US20250022866A1

    公开(公告)日:2025-01-16

    申请号:US18409931

    申请日:2024-01-11

    Abstract: A semiconductor package includes a substrate, a passive element on the substrate, and a connection terminal connecting the substrate to the passive element. The substrate includes a base portion comprising an element pad connected to the connection terminal, and an upper insulating layer on the base portion to expose at least a portion of the base portion. The passive element is in contact with the upper insulating layer, and a thickness of the connection terminal and a thickness of the upper insulating layer are equal to each other.

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES

    公开(公告)号:US20250132203A1

    公开(公告)日:2025-04-24

    申请号:US18758118

    申请日:2024-06-28

    Abstract: A method for manufacturing a semiconductor device. The method may include forming an insulating interlayer on a substrate, forming tungsten patterns inside and on the insulating interlayer, forming an insulation pattern on the insulating interlayer to fill a space between the tungsten patterns, and the insulation pattern having a lowest point of an upper surface lower than an upper surface of each of the tungsten patterns, forming a preliminary tungsten oxide layer on the upper surface of each of the tungsten patterns, performing a first surface plasma treatment on the preliminary tungsten oxide layer to remove at least a portion of the preliminary tungsten oxide layer to form a tungsten oxide layer and a protective layer on the tungsten oxide layer, and forming an etch stop layer on the protective layer and the insulation pattern.

    EPITAXIAL WAFER AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME

    公开(公告)号:US20230141135A1

    公开(公告)日:2023-05-11

    申请号:US17977013

    申请日:2022-10-31

    CPC classification number: H01L29/7843 H01L27/10805 H01L29/155

    Abstract: An epitaxial wafer and a semiconductor memory device, the epitaxial wafer including a semiconductor substrate having a front surface and a rear surface opposite to each other; a strain relaxed buffer (SRB) layer on and entirely covering the front surface of the semiconductor substrate; and a multi-stack on and entirely covering a surface of the SRB layer, wherein the SRB layer includes a silicon germanium (SiGe) epitaxial layer including germanium (Ge) at a first concentration of about 2.5 at % to about 18 at %, and the multi-stack has a superlattice structure in which a plurality of silicon (Si) layers and a plurality of SiGe layers are alternately provided.

    INTERPOSERS AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME

    公开(公告)号:US20220093519A1

    公开(公告)日:2022-03-24

    申请号:US17306290

    申请日:2021-05-03

    Abstract: A semiconductor package includes a first package substrate; a first semiconductor chip on the first package substrate; a first conductive connector on the first package substrate; and an interposer including a central portion on the first semiconductor chip and an outer portion having the first conductive connector attached thereto. The central portion of the interposer includes a bottom surface defining a recess from a bottom surface of the outer portion of the interposer in a vertical direction that is perpendicular to a top surface of the first package substrate. A thickness in the vertical direction of the outer portion of the interposer is greater than a thickness in the vertical direction of the central portion of the interposer.

Patent Agency Ranking