公开(公告)号：US20240114675A1

公开(公告)日：2024-04-04

申请号：US18541566

申请日：2023-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Han ,  Je Min Park

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033 ,  H10B12/34

Abstract: A semiconductor memory device comprises a substrate, first and second lower electrode groups on the substrate and including a plurality of first and second lower electrodes, respectively, and first and second support patterns on side walls of and connecting each of the first and second lower electrodes, respectively. The first lower electrodes include a first center lower electrode arranged within a hexagonal shape defined by first edge lower electrodes. The second lower electrodes include a second center lower electrode arranged within a hexagonal shape defined by second edge lower electrodes. The first center lower electrode is spaced apart from each of the first edge lower electrodes in different first to third directions. The first support pattern is immediately adjacent to the second support pattern. The first center lower electrode is spaced apart from the second center lower electrode in a fourth direction different from the first to third directions.

公开(公告)号：US20240063279A1

公开(公告)日：2024-02-22

申请号：US18496336

申请日：2023-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doosan Back ,  Dongoh Kim ,  Gyuhyun Kil ,  Jung-Hoon Han

IPC: H01L29/423 ,  H01L29/417 ,  H01L29/51

CPC classification number: H01L29/42368 ,  H01L29/41725 ,  H01L29/513

Abstract: A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

公开(公告)号：US11587897B2

公开(公告)日：2023-02-21

申请号：US17143224

申请日：2021-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongwon Shin ,  Yeonjin Lee ,  Inyoung Lee ,  Jimin Choi ,  Jung-Hoon Han

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/00

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a conductive pad on a first surface of the semiconductor substrate, a passivation layer on the first surface of the semiconductor substrate, the passivation layer having a first opening that exposes the conductive pad, an organic dielectric layer on the passivation layer, the organic dielectric layer having a second opening, and a bump structure on the conductive pad and in the first and second openings. The organic dielectric layer includes a material different from a material of the passivation layer. The second opening is spatially connected to the first opening and exposes a portion of the passivation layer. The bump structure includes a pillar pattern in contact with the passivation layer and the organic dielectric layer.

公开(公告)号：US11476220B2

公开(公告)日：2022-10-18

申请号：US17146550

申请日：2021-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimin Choi ,  Jung-Hoon Han ,  Yeonjin Lee ,  Jong-Min Lee ,  Jihoon Chang

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L21/66

Abstract: Semiconductor packages may include a semiconductor chip on a substrate and an under-fill layer between the semiconductor chip and the substrate. The semiconductor chip may include a semiconductor substrate including first and second regions, and an interlayer dielectric layer that may cover the semiconductor substrate and may include connection lines. First conductive pads may be on the first region and may be electrically connected to some of the connection lines. Second conductive pads may be on the second region and may be electrically isolated from all of the connection lines. The semiconductor chip may also include a passivation layer that may cover the interlayer dielectric layer and may include holes that may expose the first and second conductive pads, respectively. On the second region, the under-fill layer may include a portion that may be in one of the first holes and contact one of the second conductive pads.

公开(公告)号：US11251070B2

公开(公告)日：2022-02-15

申请号：US17016537

申请日：2020-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiseok Hong ,  Chan-Sic Yoon ,  Ilyoung Moon ,  Jemin Park ,  Kiseok Lee ,  Jung-Hoon Han

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A method of fabricating a semiconductor device includes providing a substrate, and forming an interlayered insulating layer on the substrate. The method includes forming a preliminary via hole in the interlayered insulating layer. The method includes forming a passivation spacer on an inner side surface of the preliminary via hole. The method includes forming a via hole using the passivation spacer as an etch mask. The method includes forming a conductive via in the via hole. The passivation spacer includes an insulating material different from an insulating material included in the interlayered insulating layer.

公开(公告)号：US10020288B2

公开(公告)日：2018-07-10

申请号：US15246586

申请日：2016-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Sik Park ,  Jung-Hoon Han

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor chip is provided including an integrated circuit on a substrate; pads electrically connected to the integrated circuit; a lower insulating structure defining contact holes exposing the pads, respectively; and first, second and third conductive patterns electrically connected to the pads. The second conductive pattern is between the first conductive pattern and the third conductive pattern when viewed from a plan view. Each of the first to third conductive patterns includes a contact portion filling the contact hole, a first conductive line portion extending in one direction on the lower insulating structure, and a bonding pad portion. Ends of the bonding pad portions of the first and third conductive patterns protrude in the one direction as compared with an end of the bonding pad portion of the second conductive pattern when viewed from a plan view.

公开(公告)号：US12238921B2

公开(公告)日：2025-02-25

申请号：US18541566

申请日：2023-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Han ,  Je Min Park

IPC: H10B12/00

Abstract: A semiconductor memory device comprises a substrate, first and second lower electrode groups on the substrate and including a plurality of first and second lower electrodes, respectively, and first and second support patterns on side walls of and connecting each of the first and second lower electrodes, respectively. The first lower electrodes include a first center lower electrode arranged within a hexagonal shape defined by first edge lower electrodes. The second lower electrodes include a second center lower electrode arranged within a hexagonal shape defined by second edge lower electrodes. The first center lower electrode is spaced apart from each of the first edge lower electrodes in different first to third directions. The first support pattern is immediately adjacent to the second support pattern. The first center lower electrode is spaced apart from the second center lower electrode in a fourth direction different from the first to third directions.

公开(公告)号：US11626377B2

公开(公告)日：2023-04-11

申请号：US17361588

申请日：2021-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon Han ,  Dong-Wan Kim ,  Dongho Kim ,  Jaewon Seo

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/67

Abstract: A semiconductor device includes a semiconductor substrate including a chip region and an edge region around the chip region, a lower insulating layer on the semiconductor substrate, a chip pad on the lower insulating layer on the chip region, an upper insulating layer provided on the lower insulating layer to cover the chip pad, the upper and different insulating layers including different materials, and a redistribution chip pad on the chip region and connected to the chip pad. The upper insulating layer includes a first portion on the chip region having a first thickness, a second portion on the edge region having a second thickness, and a third portion on the edge region, the third portion extending from the second portion, spaced from the first portion, and having a decreasing thickness away from the second portion. The second thickness is smaller than the first thickness.

公开(公告)号：US11075183B2

公开(公告)日：2021-07-27

申请号：US16455788

申请日：2019-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Ik Lee ,  Dong-Wan Kim ,  Seokho Shin ,  Jung-Hoon Han ,  Sang-Oh Park

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/18 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522

Abstract: A semiconductor device includes a semiconductor substrate and a connection terminal, including a base pillar, on the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, the insulation layer including an opening in the insulation layer through which the base pillar extends, wherein a side wall of the insulation layer defining the opening includes a horizontal step at a level that is lower than an uppermost portion of the base pillar.

公开(公告)号：US10950523B2

公开(公告)日：2021-03-16

申请号：US16426612

申请日：2019-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Wan Kim ,  Jung-Hoon Han ,  Dong-Sik Park

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/768

Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.