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    Voltage controlled oscillator and phase locked loop including the same
    1.
    发明授权
    Voltage controlled oscillator and phase locked loop including the same 有权
    压控振荡器和锁相环包括相同的

    公开(公告)号：US09172328B2

    公开(公告)日：2015-10-27

    申请号：US14504875

    申请日：2014-10-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Hun Lee ,  Jong-Shin Shin

    IPC: H03L7/06 ,  H03B7/06 ,  H03L7/089 ,  H03L7/099

    CPC classification number: H03B7/06 ,  H03B5/1215 ,  H03B5/1225 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1278 ,  H03B5/1287 ,  H03J1/005 ,  H03J2200/10 ,  H03L7/089 ,  H03L7/099

    Abstract: A voltage controlled oscillator (VCO) includes an oscillation frequency signal generation circuit and a transconductance control circuit. The oscillation frequency signal generation circuit has a first transconductance and generates a first oscillation frequency signal and a second oscillation frequency signal based on a voltage control signal and a power supply voltage. The first and second oscillation frequency signals are a pair of differential signals. The oscillation frequency signal generation circuit is configured to output the first oscillation frequency signal from a first output node. The oscillation frequency signal generation circuit is configured to output the second oscillation frequency signal from a second output node. The transconductance control circuit is connected to the first and second output nodes and has a second transconductance. The transconductance control circuit is configured to adjust the second transconductance based on a digital control signal.

    Abstract translation: 压控振荡器（VCO）包括振荡频率信号发生电路和跨导控制电路。 振荡频率信号发生电路具有第一跨导，并且基于电压控制信号和电源电压产生第一振荡频率信号和第二振荡频率信号。 第一和第二振荡频率信号是一对差分信号。 振荡频率信号发生电路被配置为从第一输出节点输出第一振荡频率信号。 振荡频率信号发生电路被配置为从第二输出节点输出第二振荡频率信号。 跨导控制电路连接到第一和第二输出节点并且具有第二跨导。 跨导控制电路被配置为基于数字控制信号调整第二跨导。

    Transmitting circuit and transceiver system including the same
    2.
    发明授权
    Transmitting circuit and transceiver system including the same 有权
    发射电路和收发系统包括相同的

    公开(公告)号：US09350395B2

    公开(公告)日：2016-05-24

    申请号：US14561189

    申请日：2014-12-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Aram Martirosyan ,  Jong-Shin Shin

    IPC: H04L25/03 ,  H04B1/04 ,  H04B1/40

    CPC classification number: H04B1/0475 ,  H03F3/2171 ,  H03F3/245 ,  H03F3/45139 ,  H03F2203/45481 ,  H04B1/40

    Abstract: A transmitting circuit includes a positive differential node, a negative differential node, a voltage mode driver, and a current mode driver. The voltage mode driver generates a first positive differential signal and a first negative differential signal. The voltage mode driver provides the first positive differential signal to the positive differential node and provides the first negative differential signal to the negative differential node. The current mode driver generates a second positive differential signal and a second negative differential signal. The current mode driver provides the second positive differential signal to the positive differential node and provides the second negative differential signal to the negative differential node. A differential signal voltage swing width between the positive differential node and the negative differential node is based at least on the operational state of the current mode driver and/or the voltage mode driver.

    Abstract translation: 发送电路包括正差分节点，负差分节点，电压模式驱动器和当前模式驱动器。 电压模式驱动器产生第一正差分信号和第一负差分信号。 电压模式驱动器将第一正差分信号提供给正差分节点，并将第一负差分信号提供给负差分节点。 电流模式驱动器产生第二正差分信号和第二负差分信号。 电流模式驱动器向正差分节点提供第二正差分信号，并将第二负差分信号提供给负差分节点。 至少在当前模式驱动器和/或电压模式驱动器的操作状态下，正差动节点和负差动节点之间的差分信号电压摆幅宽度是至关重要的。

    Method for driving SERDES circuit
    5.
    发明授权
    Method for driving SERDES circuit 有权
    SERDES电路驱动方法

    公开(公告)号：US09537496B2

    公开(公告)日：2017-01-03

    申请号：US14712261

    申请日：2015-05-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hwang-Ho Choi ,  Jong-Shin Shin ,  Seung-Hee Yang ,  Chang-Kyung Seong

    IPC: H03D3/24 ,  H03L7/18 ,  H03M9/00 ,  H04L1/00

    CPC classification number: H03L7/18 ,  H03M9/00 ,  H04L1/00

    Abstract: Provided is a method for driving a SERDES circuit, which may reduce waste of a space of the SERDES circuit. The circuit driving method includes generating a common clock signal from a common phase locked loop (PLL) supplying a clock signal to a serializer/deserializer (SERDES) circuit, distributing the common clock signal to an eye opening monitor and a data transmission lane in the SERDES circuit, and driving the eye opening monitor and the data transmission lane using the common clock signal.

    Abstract translation: 提供了一种用于驱动SERDES电路的方法，其可以减少SERDES电路的空间的浪费。 电路驱动方法包括从向串行器/解串器（SERDES）电路提供时钟信号的公共锁相环（PLL）产生公共时钟信号，将公共时钟信号分配给睁眼监视器和数据传输通道 SERDES电路，并使用公共时钟信号驱动睁眼监视器和数据传输通道。

    Clock data recovery circuit, timing controller including the same, and method of driving the timing controller
    6.
    发明授权
    Clock data recovery circuit, timing controller including the same, and method of driving the timing controller 有权
    时钟数据恢复电路，包括其的定时控制器以及驱动定时控制器的方法

    公开(公告)号：US09436213B2

    公开(公告)日：2016-09-06

    申请号：US14219488

    申请日：2014-03-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Du-Ho Kim ,  Jong-Shin Shin

    IPC: G06F1/12

    CPC classification number: G06F1/12

    Abstract: Provided is a clock data recovery circuit including a phase-frequency detector configured to detect a frequency and phase of a reference clock signal and control a frequency and phase of an internal clock signal based on the detected frequency, a frequency detector configured to detect a frequency of a data signal and, based on the detected frequency of the data signal, adjust the frequency of the internal clock signal; and a phase detector configured to detect a phase of the data signal based on the detected frequency of the data signal and adjust the phase of the internal clock signal. Accordingly, a timing controller that includes the clock data recovery circuit is capable of establishing data communication at high speeds when the system is powered on/off to reduce power consumption. Also, the timing controller does not need to include an additional external clock generation device, and is capable of achieving frequency synchronization using a non-precision clock signal generated in the timing controller.

    Abstract translation: 提供了一种时钟数据恢复电路，其包括：相位频率检测器，被配置为检测参考时钟信号的频率和相位，并且基于检测到的频率来控制内部时钟信号的频率和相位;频率检测器，被配置为检测频率 并且基于检测到的数据信号的频率来调整内部时钟信号的频率; 以及相位检测器，被配置为基于检测到的数据信号的频率来检测数据信号的相位，并调整内部时钟信号的相位。 因此，包括时钟数据恢复电路的定时控制器能够在系统通电/断开时以高速建立数据通信以降低功耗。 此外，定时控制器不需要包括附加的外部时钟生成装置，并且能够使用在定时控制器中生成的非精度时钟信号来实现频率同步。

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