公开(公告)号：US09742596B2

公开(公告)日：2017-08-22

申请号：US15079185

申请日：2016-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Prateek Kumar Goyal ,  Kang-Jik Kim ,  Jae-Hyun Park ,  Chang-Kyung Seong ,  Hwang-Ho Choi

IPC: H03H7/30 ,  H03H7/40 ,  H03K7/00 ,  H04L25/03 ,  H04L25/06

CPC classification number: H04L25/03057 ,  H04L25/03146 ,  H04L25/03878 ,  H04L25/03885 ,  H04L25/069

Abstract: A decision feedback equalizer includes a positive signal line, a negative signal line, a sense amplifier, a feedback driver, a load unit, a differential driver, and a charge pump. The differential driver maintains a difference between the first voltage of the positive signal line and the second voltage of the negative signal line at a last time point of the normal period to be equal to or greater than the reference voltage by adjusting strength of the positive input current corresponding to a positive input signal and strength of the negative input current corresponding to a negative input signal based on a temperature signal. The charge pump provides a positive offset voltage and a negative offset voltage to the positive signal line and the negative signal line, respectively. The positive offset voltage and the negative offset voltage are used to maintain an average voltage of the first voltage and the second voltage at the last time point of the normal period at a first value.

公开(公告)号：US09537496B2

公开(公告)日：2017-01-03

申请号：US14712261

申请日：2015-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwang-Ho Choi ,  Jong-Shin Shin ,  Seung-Hee Yang ,  Chang-Kyung Seong

IPC: H03D3/24 ,  H03L7/18 ,  H03M9/00 ,  H04L1/00

CPC classification number: H03L7/18 ,  H03M9/00 ,  H04L1/00

Abstract: Provided is a method for driving a SERDES circuit, which may reduce waste of a space of the SERDES circuit. The circuit driving method includes generating a common clock signal from a common phase locked loop (PLL) supplying a clock signal to a serializer/deserializer (SERDES) circuit, distributing the common clock signal to an eye opening monitor and a data transmission lane in the SERDES circuit, and driving the eye opening monitor and the data transmission lane using the common clock signal.

Abstract translation: 提供了一种用于驱动SERDES电路的方法，其可以减少SERDES电路的空间的浪费。 电路驱动方法包括从向串行器/解串器（SERDES）电路提供时钟信号的公共锁相环（PLL）产生公共时钟信号，将公共时钟信号分配给睁眼监视器和数据传输通道 SERDES电路，并使用公共时钟信号驱动睁眼监视器和数据传输通道。