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公开(公告)号：US20190132008A1
公开(公告)日：2019-05-02
申请号：US15956960
申请日：2018-04-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae Hun JANG , Dong-Min SHIN , Heon Hwa CHEONG , Jun Jin KONG , Hong Rak SON , Se Jin LIM
Abstract: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.
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2.发明申请公开(公告)号：US20250139194A1
公开(公告)日：2025-05-01
申请号：US18823847
申请日：2024-09-04
Applicant: Samsung Electronics Co., Ltd. , NAVER CORPORATION
Inventor： Younho JEON , Hong Rak SON , Wonsuk SONG , Younggeon YOO , JongYoon YOON , Jihoon LIM , Jae Hun JANG , Sejung KWON , Byeoungwook KIM , Baeseong PARK , Dongsoo LEE
Abstract: A matrix multiplier includes an input vector scaler configured to generate a first scaled input vector based on a first input vector and a plurality of quantization scale coefficients, a first data type converter configured to generate a first fixed-point scaled input vector based on the first scaled input vector, a processing element array including a first processing element configured to generate a first fixed-point output element based on the first fixed-point scaled input vector and first plurality of quantization sign values and a second processing element configured to generate a second fixed-point output element based on the first fixed-point scaled input vector and second plurality of quantization sign values, and a second data type converter configured to generate first and second output elements by converting data type of the first and second fixed-point output elements, and to output a first output vector including the first and second output elements.
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公开(公告)号：US20240289267A1
公开(公告)日：2024-08-29
申请号：US18384646
申请日：2023-10-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dohyeon KIM , Hong Rak SON , Jae Hun JANG , Mankeun SEO , Yong Ho SONG
IPC: G06F12/02
CPC classification number: G06F12/023
Abstract: The present disclosure provides method and apparatuses for managing memory of storage system. In some embodiments, a controller of a storage system includes a memory storing a program, and a processor configured to execute the program to determine whether a type of data stored in the memory is at least one of a first data type and a second data type, store, in the memory, a header of the data stored in the memory, based on a first determination that the data stored in the memory is of the first data type, compress the data stored in the memory, based on a second determination that data stored in the memory is of the second data type, and power off the memory based on at least one of the header of the data and the compressed data having been stored in the memory.
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公开(公告)号：US20250139193A1
公开(公告)日：2025-05-01
申请号：US18820372
申请日：2024-08-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Younho JEON , Jae Hun JANG , Suchang KIM , Yeo-Reum PARK , Hong Rak SON , Jihoon LIM , Se Jung KWON , Byeoung Wook KIM , Baeseong PARK , Dongsoo LEE
IPC: G06F17/16
Abstract: A matrix multiplier includes an input vector scaler generating a first quantization scaled input vector based on a first input vector, a plurality of common scale coefficients, and first-to-Rth multiplication scale coefficients, a first data type converter generating a first fixed point quantization scaled input vector based on the first quantization scaled input vector, an element array comprising a first processing element generating a first fixed point output element based on the first fixed point quantization scaled input vector and first plurality of quantization sign bits, and a second processing element generating a second fixed point output element based on the first fixed point quantization scaled input vector and second plurality of quantization sign bits, and a second data type converter generating and outputting first and second output elements by converting data types of the first and second fixed point output elements.
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Patent Agency Ranking
公开(公告)号：US20250117257A1
公开(公告)日：2025-04-10
申请号：US18830998
申请日：2024-09-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byungmin AHN , Hong Rak SON , Dong-Min SHIN , Dae-Yeol YANG , JongYoon YOON , Jae Hun JANG , Se Jung KWON , Byeongwook KIM , Baeseong PARK , Dongsoo LEE
Abstract: Disclosed is an accelerator device which includes an interface circuit that communicates with an external device, a memory that stores first data received through the interface circuit, a polar encoder that performs polar encoding with respect to the first data provided from the memory and to output a result of the polar encoding as second data, and an accelerator core that loads the second data. The first data are compressed weight data, the second data are decompressed weight data, the accelerator core is configured to perform machine learning-based inference based on the second data, and the first data are variable in length.
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公开(公告)号：US20250103288A1
公开(公告)日：2025-03-27
申请号：US18818742
申请日：2024-08-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae Hun JANG , Hong Rak SON , Dong-Min SHIN , JongYoon YOON , Younho JEON , Sejung KWON , Byeoungwook KIM , Baeseong PARK , Mankeun SEO , Byungmin AHN , Dongsoo LEE
Abstract: Disclosed is an accelerator performing an accumulation operation on a plurality of data, each being a floating point type. A method of operating the accelerator includes loading first data, finding a first exponent, which is a maximum value among exponents of the first data, generating aligned first fractions by performing a bit shift on first fractions of the first data based on the first exponent, and generating a first accumulated value by an accumulation operation on the aligned first fractions, loading second data, finding a second exponent, which is a maximum value among exponents of the second data, and generating a first aligned accumulated value by a bit shift on the first accumulated value, generating aligned second fractions by a bit shift on second fractions of the second data, and generating a second accumulated value by an accumulation operation on the aligned second fractions and the first aligned accumulated value.
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公开(公告)号：US20250117440A1
公开(公告)日：2025-04-10
申请号：US18817733
申请日：2024-08-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae Hun JANG , Hong Rak SON , Dong-Min SHIN , JongYoon YOON , Jihoon LIM , Younho JEON , Dongsoo LEE , Sejung KWON , Byeoungwook KIM , Baeseong PARK
Abstract: At least one embodiment provides a computing device including: a controller that receives first input data of a first data type and second input data of a second data type different from the first data type, and outputs a first signal representing the first data type, a second signal representing the second data type, and a clock signal based on the number of bits of the first input data and the second input data, and a computing circuit that performs a multiplication computation the first input data and the second input data based on the first signal, the second signal, and the clock signal and generates output data.
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8.发明公开公开(公告)号：US20230185452A1
公开(公告)日：2023-06-15
申请号：US17865621
申请日：2022-07-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngsuk RA , Hanbyeul NA , Kwanwoo NOH , Mankeun SEO , Hong Rak SON , Jae Hun JANG
IPC: G06F3/06
CPC classification number: G06F3/0608 , G06F3/0655 , G06F3/0679
Abstract: A method of operating a storage controller includes receiving raw data indicating a series of bits each corresponding to one of threshold voltage states, performing a first state shaping for reducing a number of first target bits of the series of bits, logical values of the first target bits being equal to a logical value of a target threshold voltage state of the threshold voltage states in a first page of plural pages, generating first indicator data that indicates the first target bits based on the first state shaping, compressing the first indicator data, and storing the compressed first indicator data.
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公开(公告)号：US20210281280A1
公开(公告)日：2021-09-09
申请号：US17314768
申请日：2021-05-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae Hun JANG , Dong-Min SHIN , Heon Hwa CHEONG , Jun Jin KONG , Hong Rak SON , Se Jin LIM
Abstract: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.
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