公开(公告)号：US20250126792A1

公开(公告)日：2025-04-17

申请号：US18990188

申请日：2024-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhwan LIM ,  Nambin KIM ,  Samki KIM ,  Taehun KIM ,  Hanvit YANG ,  Changhee LEE ,  Jaehun JUNG ,  Hyeongwon CHOI

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a lower structure including a semiconductor substrate and circuit devices on the semiconductor substrate; a stack structure including interlayer insulating layers and gate electrodes alternating in a vertical direction; and a channel structure penetrating the stack structure. The channel structure includes a core insulating layer, a channel layer, a gate dielectric layer, and a channel pad. A portion of the channel pad overlaps an uppermost gate electrode among the gate electrodes in a horizontal direction. The channel pad includes a first pad layer and a second pad layer on the first pad layer. The second pad layer includes doped polysilicon that is doped with impurities and having N-type conductivity. The first pad layer includes at least one of an undoped polysilicon region and a doped polysilicon region having N-type conductivity and having an impurity concentration lower than an impurity concentration of the second pad layer.

公开(公告)号：US20240121958A1

公开(公告)日：2024-04-11

申请号：US18243200

申请日：2023-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Samki KIM ,  Nambin KIM ,  Taehun KIM ,  Suhwan LIM ,  Hyeongwon CHOI

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A vertical semiconductor device includes; a pattern structure including a plurality of insulation patterns and a plurality of gate electrodes that are alternately and repeatedly stacked on a substrate, wherein the pattern structure includes a first gate electrode serving as a gate electrode of an erase transistor, wherein the first gate electrode is one of the plurality of gate electrodes; and a channel structure in a channel hole passing through the pattern structure, wherein the channel structure includes a data storage structure, a first channel, an undoped semiconductor liner, a doped semiconductor pattern, a filling insulation pattern and a capping pattern, wherein the data storage structure, the first channel, the undoped semiconductor liner, and the doped semiconductor pattern are sequentially disposed on a sidewall of the first gate electrode.

公开(公告)号：US20230035421A1

公开(公告)日：2023-02-02

申请号：US17720376

申请日：2022-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhwan LIM ,  Nambin KIM ,  Samki KIM ,  Taehun KIM ,  Hanvit YANG ,  Changhee LEE ,  Jaehun JUNG ,  Hyeongwon CHOI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11526

Abstract: A semiconductor device includes a lower structure including a semiconductor substrate and circuit devices on the semiconductor substrate; a stack structure including interlayer insulating layers and gate electrodes alternating in a vertical direction; and a channel structure penetrating the stack structure. The channel structure includes a core insulating layer, a channel layer, a gate dielectric layer, and a channel pad. A portion of the channel pad overlaps an uppermost gate electrode among the gate electrodes in a horizontal direction. The channel pad includes a first pad layer and a second pad layer on the first pad layer. The second pad layer includes doped polysilicon that is doped with impurities and having N-type conductivity. The first pad layer includes at least one of an undoped polysilicon region and a doped polysilicon region having N-type conductivity and having an impurity concentration lower than an impurity concentration of the second pad layer.