公开(公告)号：US20210050508A1

公开(公告)日：2021-02-18

申请号：US16829216

申请日：2020-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seowon LEE ,  Junghwan MOON ,  Junghoon BAK ,  Woojin KIM ,  Hyeongsun HONG

IPC: H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L43/10 ,  H01F10/32

Abstract: A magnetic memory device includes a device isolation layer on a substrate and defining an active region, a source region and a drain region apart from each other in the active region of the substrate, a channel portion in the active region of the substrate and between the source region and the drain region, a spin orbit torque (SOT)-inducing layer on the channel portion of the substrate, a magnetic tunnel junction (MTJ) structure on the SOT-inducing layer, the MTJ structure including a free layer on the SOT-inducing layer, a tunnel barrier layer on the free layer, and a pinned layer on the tunnel barrier, a word line on the MTJ structure, a source line electrically connected to the source region, and a bit line electrically connected to the drain region.

公开(公告)号：US20150055401A1

公开(公告)日：2015-02-26

申请号：US14537387

申请日：2014-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung KIM ,  Yongchul OH ,  Dongsoo WOO ,  Hyun-Woo CHUNG ,  Gyoyoung JIN ,  Sungkwan CHOI ,  Hyeongsun HONG ,  Yoosang HWANG

IPC: G11C11/4096 ,  G11C11/404 ,  H01L29/66 ,  H01L27/108 ,  H01L29/423

CPC classification number: G11C11/4096 ,  G11C11/404 ,  G11C11/4085 ,  H01L21/823437 ,  H01L27/10823 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.

Abstract translation: 半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。 更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。 此外，第一和第二栅电极可以是电隔离的。 还讨论了相关设备，结构，操作方法和制造方法。