公开(公告)号：US10186519B2

公开(公告)日：2019-01-22

申请号：US15059993

申请日：2016-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwon Kim ,  Hyeong Park ,  Hyunmin Lee ,  Hojong Kang ,  Joowon Park ,  Seungmin Song

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

Abstract: A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.

公开(公告)号：US09553098B2

公开(公告)日：2017-01-24

申请号：US14858756

申请日：2015-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Hyun You ,  Hyeong Park ,  Bongtae Park ,  Jeehoon Han

IPC: H01L27/115 ,  H01L23/528 ,  H01L23/532 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L23/528 ,  H01L23/53209 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L29/42324 ,  H01L29/4933 ,  H01L29/513 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns. The remaining line patterns include second end-portions adjacent to the lines. The first end-portions and second end-portions are formed to have mirror symmetry with respect to each other.

Abstract translation: 半导体器件包括设置在半导体衬底上的多条线，以及与线路延伸线上间隔开的剩余线图案。 这些线包括与其余线图案相邻的第一端部。 剩余的线图案包括与线相邻的第二端部。 第一端部和第二端部形成为相对于彼此具有镜像对称性。

公开(公告)号：US09171853B2

公开(公告)日：2015-10-27

申请号：US14200610

申请日：2014-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang-Hyun You ,  Hyeong Park ,  Bongtae Park ,  Jeehoon Han

IPC: H01L27/115

CPC classification number: H01L27/11521 ,  H01L23/528 ,  H01L23/53209 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L29/42324 ,  H01L29/4933 ,  H01L29/513 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns. The remaining line patterns include second end-portions adjacent to the lines. The first end-portions and second end-portions are formed to have mirror symmetry with respect to each other.

Abstract translation: 半导体器件包括设置在半导体衬底上的多条线，以及与线路延伸线上间隔开的剩余线图案。 这些线包括与其余线图案相邻的第一端部。 剩余的线图案包括与线相邻的第二端部。 第一端部和第二端部形成为相对于彼此具有镜像对称性。

公开(公告)号：US11925015B2

公开(公告)日：2024-03-05

申请号：US17024987

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yong Park ,  Kee-Jeong Rho ,  Hyeong Park ,  Tae-Wan Lim

IPC: H10B12/00 ,  H01L23/31 ,  H01L23/528 ,  H01L29/423 ,  H01L29/78 ,  H01L29/792 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B12/50 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/528 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/7827 ,  H01L29/7926 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

公开(公告)号：US10685977B2

公开(公告)日：2020-06-16

申请号：US16231710

申请日：2018-12-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwon Kim ,  Hyeong Park ,  Hyunmin Lee ,  Hojong Kang ,  Joowon Park ,  Seungmin Song

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

Abstract: A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.