公开(公告)号：US20220343957A1

公开(公告)日：2022-10-27

申请号：US17526398

申请日：2021-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Youngchul Cho ,  Youngdon Choi ,  Changsik Yoo ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/10

Abstract: A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

公开(公告)号：US20220336004A1

公开(公告)日：2022-10-20

申请号：US17508598

申请日：2021-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Wonjoo Jung ,  Jaewoo Park ,  Youngchul Cho ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C11/4076 ,  H01L25/065

Abstract: A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.

公开(公告)号：US12293801B2

公开(公告)日：2025-05-06

申请号：US18200709

申请日：2023-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hojun Yoon ,  Youngdon Choi ,  Seungjin Park ,  Seunghoon Lee ,  Junghwan Choi

IPC: G11C29/12 ,  G11C7/22 ,  G11C8/18 ,  H03K5/156

Abstract: A semiconductor device has a memory controller configured to provide a data strobe signal, and a memory device configured to receive a data signal provided from the memory controller or output a data signal to the memory controller, wherein the memory device includes a memory interface including a plurality of DQ driving circuits, the memory interface being configured to generate a plurality of phase clock signals based on the data strobe signal, determine a number of phase clock signals provided to the plurality of DQ driving circuits based on an operating frequency of the memory device, and provide the determined number of phase clock signals to the plurality of DQ driving circuits.

公开(公告)号：US12009057B2

公开(公告)日：2024-06-11

申请号：US18143967

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Youngchul Cho ,  Youngdon Choi ,  Changsik Yoo ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084

Abstract: A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

公开(公告)号：US20230307022A1

公开(公告)日：2023-09-28

申请号：US18143967

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Youngchul Cho ,  Youngdon Choi ,  Changsik Yoo ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084

Abstract: A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

公开(公告)号：US11742016B2

公开(公告)日：2023-08-29

申请号：US17508598

申请日：2021-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Wonjoo Jung ,  Jaewoo Park ,  Youngchul Cho ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C7/22 ,  G11C11/4076 ,  G11C29/02 ,  H03K5/156 ,  H03K5/12

CPC classification number: G11C11/4076 ,  G11C7/222 ,  G11C29/023 ,  H03K5/1565 ,  G11C29/028 ,  H03K5/12

Abstract: A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.

公开(公告)号：US12057156B2

公开(公告)日：2024-08-06

申请号：US18218243

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Wonjoo Jung ,  Jaewoo Park ,  Youngchul Cho ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C7/22 ,  G11C11/4076 ,  G11C29/02 ,  H03K5/156 ,  H03K5/12

CPC classification number: G11C11/4076 ,  G11C7/222 ,  G11C29/023 ,  H03K5/1565 ,  G11C29/028 ,  H03K5/12

Abstract: A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.

公开(公告)号：US20240046999A1

公开(公告)日：2024-02-08

申请号：US18148579

申请日：2022-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Seungjin Park ,  Doobock Lee ,  Seunghoon Lee ,  Baek Jin Lim ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C16/32 ,  G11C16/04 ,  G06F1/10

CPC classification number: G11C16/32 ,  G11C16/0483 ,  G06F1/10

Abstract: A nonvolatile memory device may include a variable sampler configured to process a data signal in an amplifier mode or a sampler mode in response to a control signal, a selection circuit configured to transmit the data signal output from the variable sampler to a flip-flop via a delay unit or to the flip-flop via a path that bypasses the delay unit in response to the control signal, a converter configured to amplify a data strobe signal, a clock distribution network configured to transmit the data strobe signal amplified by the converter to the variable sampler or delay the amplified data strobe signal for a predetermined time and transmit the amplified data strobe signal to the flip-flop in response to the control signal, and a path controller configured to generate the control signal according to an input/output mode.

公开(公告)号：US20230343383A1

公开(公告)日：2023-10-26

申请号：US18218243

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Wonjoo Jung ,  Jaewoo Park ,  Youngchul Cho ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C11/4076 ,  G11C7/22 ,  G11C29/02 ,  H03K5/156

CPC classification number: G11C11/4076 ,  G11C7/222 ,  G11C29/023 ,  H03K5/1565 ,  G11C29/028 ,  H03K5/12

Abstract: A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.

公开(公告)号：US11699472B2

公开(公告)日：2023-07-11

申请号：US17526398

申请日：2021-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Youngchul Cho ,  Youngdon Choi ,  Changsik Yoo ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084

Abstract: A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.