公开(公告)号：US11742016B2

公开(公告)日：2023-08-29

申请号：US17508598

申请日：2021-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Wonjoo Jung ,  Jaewoo Park ,  Youngchul Cho ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C7/22 ,  G11C11/4076 ,  G11C29/02 ,  H03K5/156 ,  H03K5/12

CPC classification number: G11C11/4076 ,  G11C7/222 ,  G11C29/023 ,  H03K5/1565 ,  G11C29/028 ,  H03K5/12

Abstract: A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.

公开(公告)号：US11545966B2

公开(公告)日：2023-01-03

申请号：US17224577

申请日：2021-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Choi ,  Wonjoo Jung ,  Youngchul Cho ,  Youngdon Choi ,  Junghwan Choi

IPC: H03B27/00 ,  H03K5/01

Abstract: An injection locking oscillator (ILO) circuit includes; an injection circuit that receives input signals having a phase difference and provides injection signals respectively corresponding to the input signals based on a voltage level difference between each input signal and an oscillation signal at an output terminal, and a poly-phase signal output circuit that provides poly-phased signals having a phase difference between signals fixed to a defined phase difference upon receiving the injection signals from the input terminals.

公开(公告)号：US20220336004A1

公开(公告)日：2022-10-20

申请号：US17508598

申请日：2021-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Wonjoo Jung ,  Jaewoo Park ,  Youngchul Cho ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C11/4076 ,  H01L25/065

Abstract: A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.

公开(公告)号：US12057156B2

公开(公告)日：2024-08-06

申请号：US18218243

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Wonjoo Jung ,  Jaewoo Park ,  Youngchul Cho ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C7/22 ,  G11C11/4076 ,  G11C29/02 ,  H03K5/156 ,  H03K5/12

CPC classification number: G11C11/4076 ,  G11C7/222 ,  G11C29/023 ,  H03K5/1565 ,  G11C29/028 ,  H03K5/12

Abstract: A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.

公开(公告)号：US20230343383A1

公开(公告)日：2023-10-26

申请号：US18218243

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Wonjoo Jung ,  Jaewoo Park ,  Youngchul Cho ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C11/4076 ,  G11C7/22 ,  G11C29/02 ,  H03K5/156

CPC classification number: G11C11/4076 ,  G11C7/222 ,  G11C29/023 ,  H03K5/1565 ,  G11C29/028 ,  H03K5/12

Abstract: A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.