公开(公告)号：US12137560B2

公开(公告)日：2024-11-05

申请号：US17384329

申请日：2021-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： HangKyu Kang ,  Jongsoo Kim ,  Juyoung Lim ,  Wonseok Cho

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a substrate having a first region, a second region, and a third region with gate electrodes spaced apart from each other in the first region and the second region. The semiconductor device also includes interlayer insulating layers alternately stacked with the gate electrodes, channel structures passing through the gate electrodes in the first region, first dummy structures passing through the gate electrodes in the second region, the first dummy structures disposed adjacent to the first region, second dummy structures passing through the gate electrodes in the second region, the second dummy structures disposed adjacent to the third region, and having different shapes from the first dummy structures, and support structures passing through the gate electrodes in the third region. A size of each of the second dummy structures is larger than a size of each of the support structures.

公开(公告)号：US20220189988A1

公开(公告)日：2022-06-16

申请号：US17384329

申请日：2021-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： HangKyu Kang ,  Jongsoo Kim ,  Juyoung Lim ,  Wonseok Cho

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11524 ,  H01L27/11519 ,  H01L23/528

Abstract: A semiconductor device includes a substrate having a first region, a second region, and a third region with gate electrodes spaced apart from each other in the first region and the second region. The semiconductor device also includes interlayer insulating layers alternately stacked with the gate electrodes, channel structures passing through the gate electrodes in the first region, first dummy structures passing through the gate electrodes in the second region, the first dummy structures disposed adjacent to the first region, second dummy structures passing through the gate electrodes in the second region, the second dummy structures disposed adjacent to the third region, and having different shapes from the first dummy structures, and support structures passing through the gate electrodes in the third region. A size of each of the second dummy structures is larger than a size of each of the support structures.