公开(公告)号：US20200176317A1

公开(公告)日：2020-06-04

申请号：US16785236

申请日：2020-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namgyu CHO ,  Kughwan Kim ,  Geunwoo Kim ,  Jungmin Park ,  Minwoo Song

IPC: H01L21/8234 ,  H01L29/40 ,  H01L21/3213 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device may include forming a first conductive layer on first to third regions of a substrate, forming a barrier layer on the first conductive layer, the barrier layer including a first barrier layer, a second barrier layer, and a sacrificial layer which are sequentially formed, sequentially forming a second conductive layer and a third conductive layer on the barrier layer, performing a first etching process to remove the third conductive layer from the second region and the third region, the third conductive layer remaining on the first region after the first etching process, and performing a second etching process to remove the second conductive layer and the sacrificial layer from the third region, the second conductive layer and the sacrificial layer remaining on the first region and on the second region after the second etching process.

公开(公告)号：US20240250088A1

公开(公告)日：2024-07-25

申请号：US18600403

申请日：2024-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon Tae Hwang ,  Sunjung Lee ,  Heonbok Lee ,  Geunwoo Kim ,  Wandon Kim

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871

Abstract: A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

公开(公告)号：US11955487B2

公开(公告)日：2024-04-09

申请号：US17886878

申请日：2022-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon Tae Hwang ,  Sunjung Lee ,  Heonbok Lee ,  Geunwoo Kim ,  Wandon Kim

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871

Abstract: A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

公开(公告)号：US11552392B2

公开(公告)日：2023-01-10

申请号：US16571544

申请日：2019-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmin Jung ,  Geunwoo Kim

IPC: H01Q1/52 ,  H04W76/10 ,  G06F13/38 ,  H04W88/04 ,  H04W36/00

Abstract: An electronic device comprises a plurality of antennas, wherein each of the plurality of antennas are spaced apart from each other, a first communication circuit electrically connected with the plurality of antennas, a plurality of array antennas comprising a first array antenna disposed adjacent to at least one of the plurality of antennas, and a second array antenna disposed adjacent to another antenna different from the at least one antenna of the plurality of antennas, a second communication circuit electrically connected with the first array antenna and the second array antenna, and at least one control circuit electrically connected with the first communication circuit and the second communication circuit, wherein the at least one control circuit is configured to obtain receive sensitivities of the plurality of antennas through the first communication circuit; activate at least one array antenna of the first array antenna and the second array antenna through the second communication circuit based at least on the receive sensitivities; and control the activated at least one array antenna to form at least one beam for communication with an external electronic device.

公开(公告)号：US12126685B2

公开(公告)日：2024-10-22

申请号：US17940444

申请日：2022-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwoo Kim ,  Md. Imtiaz Hossain ,  Muhammad Mushfiqul Islam ,  Towhidul Islam

IPC: H04L67/141 ,  G06F3/14 ,  H04L47/70 ,  H04L65/40 ,  H04L67/1095

CPC classification number: H04L67/141 ,  G06F3/1454 ,  H04L47/82 ,  H04L65/40 ,  H04L67/1095

Abstract: An electronic device includes a first communication module, a second communication module, a display, a processor, and a memory storing instructions causing the processor to receive, from an external electronic device connected via the first communication module, first data related to a first screen on which resources of the external electronic device are configured in accordance with a graphic environment of the electronic device, output the first screen on the display, request the external electronic device to execute a selected first resource, receive, from the external electronic device, a request for obtaining second data related to the first resource, connect to the network via the second communication module to obtain the second data, transmit the obtained second data to the external electronic device, receive, from the external electronic device, third data related to a second screen configured using the second data, and output the second screen on the display.

公开(公告)号：US11631769B2

公开(公告)日：2023-04-18

申请号：US17321960

申请日：2021-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwoo Kim ,  Wandon Kim ,  Heonbok Lee ,  Yoontae Hwang

IPC: H01L29/78 ,  H01L29/417

Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction; a gate structure extending across the fin-type active region in a second direction, different from the first direction; a source/drain region in the fin-type active region on one side of the gate structure; and first and second contact structures connected to the source/drain region and the gate structure, respectively, wherein at least one of the first and second contact structures includes a seeding layer on at least one of the gate structure and the source/drain region and including a first crystalline metal, and a contact plug on the seeding layer and including a second crystalline metal different from the first crystalline metal, and the second crystalline metal is substantially lattice-matched to the first crystalline metal at an interface between the seeding layer and the contact plug.

公开(公告)号：US11239334B2

公开(公告)日：2022-02-01

申请号：US16811605

申请日：2020-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Tae Hwang ,  Wandon Kim ,  Geunwoo Kim

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/532 ,  H01L29/08 ,  H01L21/285 ,  H01L29/45 ,  H01L29/78

Abstract: A semiconductor device including a lower contact pattern including a first metal, an upper contact pattern including a second metal, a first resistivity of first metal being greater than a second resistivity of the second metal, and a metal barrier layer between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first and second metals may be provided. A lower width of the upper contact pattern may be less than an upper width of the lower contact pattern.

公开(公告)号：US20210057533A1

公开(公告)日：2021-02-25

申请号：US16811605

申请日：2020-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Tae HWANG ,  Wandon Kim ,  Geunwoo Kim

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/532 ,  H01L29/45 ,  H01L29/08 ,  H01L21/285

Abstract: A semiconductor device including a lower contact pattern including a first metal, an upper contact pattern including a second metal, a first resistivity of first metal being greater than a second resistivity of the second metal, and a metal barrier layer between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first and second metals may be provided. A lower width of the upper contact pattern may be less than an upper width of the lower contact pattern.

公开(公告)号：US10593597B2

公开(公告)日：2020-03-17

申请号：US16185213

申请日：2018-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namgyu Cho ,  Kughwan Kim ,  Geunwoo Kim ,  Jungmin Park ,  Minwoo Song

IPC: H01L21/82 ,  H01L29/40 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213

Abstract: A method of fabricating a semiconductor device may include forming a first conductive layer on first to third regions of a substrate, forming a barrier layer on the first conductive layer, the barrier layer including a first barrier layer, a second barrier layer, and a sacrificial layer which are sequentially formed, sequentially forming a second conductive layer and a third conductive layer on the barrier layer, performing a first etching process to remove the third conductive layer from the second region and the third region, the third conductive layer remaining on the first region after the first etching process, and performing a second etching process to remove the second conductive layer and the sacrificial layer from the third region, the second conductive layer and the sacrificial layer remaining on the first region and on the second region after the second etching process.

公开(公告)号：US12183742B2

公开(公告)日：2024-12-31

申请号：US18600403

申请日：2024-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon Tae Hwang ,  Sunjung Lee ,  Heonbok Lee ,  Geunwoo Kim ,  Wandon Kim

IPC: H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.