公开(公告)号：US10431680B2

公开(公告)日：2019-10-01

申请号：US15391888

申请日：2016-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungsam Lee ,  Junsoo Kim ,  Hyoshin Ahn ,  Satoru Yamada ,  Joohyun Jeon ,  MoonYoung Jeong ,  Chunhyung Chung ,  Min Hee Cho ,  Kyo-Suk Chae ,  Eunae Choi

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/04

Abstract: A semiconductor device including a semiconductor substrate including a trench, the semiconductor substrate having a crystal structure; and an insulating layer covering an inner sidewall of the trench, wherein the inner sidewall of the trench has at least one plane included in a {320} family of planes of the crystal structure or at least one plane similar to the {320} family of planes.

公开(公告)号：US20210134975A1

公开(公告)日：2021-05-06

申请号：US16927463

申请日：2020-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Naoto Umezawa ,  Satoru Yamada ,  Junsoo Kim ,  Honglae Park ,  Chunhyung Chung

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L27/108

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes D+ and ND2+ in an interface region, adjacent the first metal layer, and D is deuterium, N is nitrogen, and D+ is positively-charged deuterium.

公开(公告)号：US10833088B2

公开(公告)日：2020-11-10

申请号：US16805585

申请日：2020-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hyun Im ,  Daehyun Kim ,  Hoon Park ,  Jae-Hong Seo ,  Chunhyung Chung ,  Jae-Joong Choi

IPC: H01L29/49 ,  H01L27/108 ,  H01L21/283 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8234

Abstract: A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.

公开(公告)号：US11830567B2

公开(公告)日：2023-11-28

申请号：US17372697

申请日：2021-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwon Ma ,  Chunhyung Chung ,  Jamin Koo ,  Kyuwan Kim ,  Daeyoung Moon ,  Wonseok Yoo

IPC: G11C5/06 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H10B12/00

CPC classification number: G11C5/063 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/532 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/482

Abstract: An integrated circuit device includes; word lines extending in a first direction across a substrate and spaced apart in a second direction different from the first direction, bit lines extending on the word lines in the second direction and spaced apart in the first direction, a first contact plug arranged among the bitlines, contacting a first active region of the substrate, having a first width, and having a first dopant concentration, and a second contact plug arranged among the bitlines, contacting a second active region of the substrate, having a second width, and having a second dopant concentration less than the first dopant concentration.

公开(公告)号：US11742401B2

公开(公告)日：2023-08-29

申请号：US17340667

申请日：2021-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmi Yoon ,  Jooyub Kim ,  Daehyun Kim ,  Juhyung We ,  Donghyun Im ,  Chunhyung Chung

IPC: H01L29/423 ,  H01L29/49 ,  H10B12/00

CPC classification number: H01L29/4236 ,  H01L29/49 ,  H10B12/053 ,  H10B12/34 ,  H10B12/488 ,  H10B12/30 ,  H10B12/315

Abstract: A semiconductor device may include a substrate including a recess, a gate insulation layer on a surface of the recess, an impurity barrier layer on a surface of the gate insulation layer to cover the surface of the gate insulation layer, a first gate pattern on impurity barrier layer to fill a lower portion of the recess, a second gate pattern on the first gate pattern in the recess, a capping insulation pattern on the second gate pattern to fill the recess, and impurity regions at the substrate adjacent to an upper sidewall of the recess. The impurity barrier layer may have a concentration of nitrogen higher than a concentration of nitrogen included in the gate insulation layer. The second gate pattern may include a material different from a material of the first gate pattern. A lower surface of the impurity regions may be higher than an upper surface of the first gate pattern. Thus, the semiconductor device may have good characteristics.

公开(公告)号：US11329137B2

公开(公告)日：2022-05-10

申请号：US16927463

申请日：2020-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Naoto Umezawa ,  Satoru Yamada ,  Junsoo Kim ,  Honglae Park ,  Chunhyung Chung

IPC: H01L29/51 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes D+ and ND2+ in an interface region, adjacent the first metal layer, and D is deuterium, N is nitrogen, and D+ is positively-charged deuterium.

公开(公告)号：US20250142812A1

公开(公告)日：2025-05-01

申请号：US18896219

申请日：2024-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suyoun Song ,  Jamin Koo ,  Beomseo Kim ,  Jonghyeok Kim ,  Daeyoung Moon ,  Changwoo Seo ,  Wonseok Yoo ,  Chunhyung Chung

IPC: H10B12/00 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including a first active region, a bit line on the substrate to cross the first active region, a bit line contact between the bit line and the first active region and in a bit line contact hole extending into the substrate, a bit line contact spacer on a sidewall of the bit line contact within the bit line contact hole, a bit line spacer on a sidewall of the bit line, an anti-oxidation layer between the sidewall of the bit line and the bit line spacer and between the sidewall of the bit line contact and the bit line spacer, and a buried contact in a buried contact hole, passing through the bit line contact spacer, and contacting the first active region, in which the anti-oxidation layer includes a silicon-containing material including SiOx, where 0

公开(公告)号：US11812607B2

公开(公告)日：2023-11-07

申请号：US17685794

申请日：2022-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmi Yoon ,  Donghyun Im ,  Jooyub Kim ,  Juhyung We ,  Namhoon Lee ,  Chunhyung Chung

IPC: H01L21/768 ,  H10B12/00 ,  H01L21/762 ,  H01L29/06

CPC classification number: H10B12/34 ,  H01L21/76224 ,  H01L21/76829 ,  H01L29/0653 ,  H10B12/053 ,  H10B12/315

Abstract: A semiconductor device may include active pattern, a silicon liner, an insulation layer, an isolation pattern and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be formed conformally on surfaces of the active pattern and the substrate. The insulation layer may be formed on the silicon liner. The isolation pattern may be formed on the insulation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be disposed on the silicon liner, and the impurity regions may be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure.

公开(公告)号：US10707216B2

公开(公告)日：2020-07-07

申请号：US16023018

申请日：2018-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmi Yoon ,  Chunhyung Chung

IPC: H01L21/336 ,  H01L27/108 ,  H01L21/762 ,  H01L21/3205 ,  H01L21/321 ,  C23C16/24 ,  H01L29/06 ,  C23C16/44 ,  C23C16/02

Abstract: Provided is a method for manufacturing a semiconductor device including: patterning a substrate to form a plurality of active patterns including two adjacent active patterns having a first trench therebetween; forming a semiconductor layer on the plurality of active patterns to cover the plurality of active patterns; forming a device isolation layer on the semiconductor layer to cover the semiconductor layer for oxidization and fill the first trench; patterning the device isolation layer and the plurality of active patterns so that a second trench intersecting the first trench is formed and the two active patterns protrudes from the device isolation layer in the second trench; and forming a gate electrode in the second trench. Here, a first thickness of the semiconductor layer covering a top surface of each of the two active patterns is greater than a second thickness of the semiconductor layer covering a bottom of the first trench.

公开(公告)号：US10373959B2

公开(公告)日：2019-08-06

申请号：US16050848

申请日：2018-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hyun Im ,  Daehyun Kim ,  Hoon Park ,  Jae-Hong Seo ,  Chunhyung Chung ,  Jae-Joong Choi

IPC: H01L29/423 ,  H01L27/108 ,  H01L21/283 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L21/8234

Abstract: A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.