公开(公告)号：US20170229581A1

公开(公告)日：2017-08-10

申请号：US15494845

申请日：2017-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun-Nam Kim ,  Hung-Mo YANG ,  Choong-Ho LEE

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7854 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7856

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

公开(公告)号：US20160141243A1

公开(公告)日：2016-05-19

申请号：US14712136

申请日：2015-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gun YOU ,  Wei-Hua HSU ,  Choong-Ho LEE ,  Hyung-Jong LEE

IPC: H01L23/522 ,  H01L27/088 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/088 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed on the first region and the second region, respectively, a first contact formed on the first transistor, and a second contact formed on the second transistor. The first contact includes a first work function control layer having a first thickness and a first conductive layer formed on the first work function control layer, the second contact includes a second work function control layer having a second thickness different from the first thickness and a second conductive layer formed on the second work function control layer, and the first contact and the second contact have different work functions.

Abstract translation: 提供半导体器件及其制造方法。 该半导体器件包括分别包括第一区域和第二区域的基板，分别形成在第一区域和第二区域上的第一晶体管和第二晶体管，形成在第一晶体管上的第一触点和形成在第一晶体管上的第二触点 第二晶体管。 第一触点包括具有第一厚度的第一功函数控制层和形成在第一功函数控制层上的第一导电层，第二触点包括具有不同于第一厚度的第二厚度的第二功函数控制层， 导电层形成在第二功函数控制层上，第一触点和第二触点具有不同的功能。

公开(公告)号：US20160056296A1

公开(公告)日：2016-02-25

申请号：US14931490

申请日：2015-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun-Nam Kim ,  Hung-Mo YANG ,  Choong-Ho LEE

IPC: H01L29/78 ,  H01L29/423

CPC classification number: H01L29/7854 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7856

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

公开(公告)号：US20150228796A1

公开(公告)日：2015-08-13

申请号：US14695672

申请日：2015-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun-Nam Kim ,  Hung-Mo YANG ,  Choong-Ho LEE

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7854 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7856

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

Abstract translation: 使用体硅衬底形成鳍状场效应晶体管（鳍FET），并通过在翅片有源区中形成具有预定深度的凹槽，然后通过在上部形成栅极来充分保证形成在栅极下方的顶部沟道长度 部分休息。 形成器件隔离膜以在衬底的预定区域中限定非有源区和鳍有源区。 在器件隔离膜的一部分中，形成第一凹部，并且在翅片有源区域的一部分中形成有比第一凹部浅的深度的第二凹部。 栅极绝缘层形成在第二凹部内，栅极形成在第二凹部的上部。 源极/漏极区域形成在栅电极的两侧的鳍片有源区域中。