公开(公告)号：US11854892B2

公开(公告)日：2023-12-26

申请号：US17699570

申请日：2022-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Jungchul Lee ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim

IPC: H01L21/78 ,  H01L21/268 ,  H01L21/683 ,  H01L21/304

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/6836 ,  H01L2221/68336

Abstract: According to an embodiment of inventive concepts, a substrate dicing method may include forming reformed patterns in a substrate using a laser beam, grinding a bottom surface of the substrate to thin the substrate, and expanding the substrate to divide the substrate into a plurality of semiconductor chips. The forming of the reformed patterns may include forming a first reformed pattern in the substrate and providing an edge focused beam to a region crossing the first reformed pattern to form a second reformed pattern in contact with the first reformed pattern.

公开(公告)号：US11676914B2

公开(公告)日：2023-06-13

申请号：US17216279

申请日：2021-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwayoung Lee ,  Heejae Nam ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim ,  Junho Yoon ,  Dongjin Lee

IPC: H01L23/544 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/544 ,  H01L2223/5446

Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.

公开(公告)号：US12062626B2

公开(公告)日：2024-08-13

申请号：US18144902

申请日：2023-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwayoung Lee ,  Heejae Nam ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim ,  Junho Yoon ,  Dongjin Lee

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/544 ,  H01L2223/5446

Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.

公开(公告)号：US20180315698A1

公开(公告)日：2018-11-01

申请号：US16029030

申请日：2018-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinGyu Kim ,  Taehun Kim ,  JiSun Hong ,  Byungmoon Bae ,  Se-Ho You

IPC: H01L23/498 ,  H01L23/60

CPC classification number: H01L23/49838 ,  H01L23/293 ,  H01L23/49816 ,  H01L23/562 ,  H01L23/60 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16237 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.

公开(公告)号：US20230275037A1

公开(公告)日：2023-08-31

申请号：US18144902

申请日：2023-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwayoung Lee ,  Heejae Nam ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim ,  Junho Yoon ,  Dongjin Lee

IPC: H01L23/00 ,  H01L23/544 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L23/544 ,  H01L21/78 ,  H01L2223/5446

Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.

公开(公告)号：US10256181B2

公开(公告)日：2019-04-09

申请号：US16029030

申请日：2018-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinGyu Kim ,  Taehun Kim ,  JiSun Hong ,  Byungmoon Bae ,  Se-Ho You

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/60 ,  H01L23/29

Abstract: A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.

公开(公告)号：US11322405B2

公开(公告)日：2022-05-03

申请号：US16909136

申请日：2020-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Jungchul Lee ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim

IPC: G11B11/105 ,  B23K26/00 ,  B23K26/40 ,  H01L21/78 ,  H01L21/268 ,  H01L21/683 ,  H01L21/304

Abstract: According to an embodiment of inventive concepts, a substrate dicing method may include forming reformed patterns in a substrate using a laser beam, grinding a bottom surface of the substrate to thin the substrate, and expanding the substrate to divide the substrate into a plurality of semiconductor chips. The forming of the reformed patterns may include forming a first reformed pattern in the substrate and providing an edge focused beam to a region crossing the first reformed pattern to form a second reformed pattern in contact with the first reformed pattern.

公开(公告)号：US20220059472A1

公开(公告)日：2022-02-24

申请号：US17216279

申请日：2021-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwayoung Lee ,  Heejae Nam ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim ,  Junho Yoon ,  Dongjin Lee

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544

Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.

公开(公告)号：US10032706B2

公开(公告)日：2018-07-24

申请号：US15236868

申请日：2016-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinGyu Kim ,  Taehun Kim ,  JiSun Hong ,  Byungmoon Bae ,  Se-Ho You

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/60 ,  H01L23/29

CPC classification number: H01L23/49838 ,  H01L23/293 ,  H01L23/49816 ,  H01L23/562 ,  H01L23/60 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16237 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.