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公开(公告)号：US10476707B2
公开(公告)日：2019-11-12
申请号：US16058896
申请日：2018-08-08
Applicant: Samsung Display Co., Ltd.
Inventor： Anup P. Jose , Amir Amirkhany , Mohammad Hekmat
Abstract: A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.
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公开(公告)号：US11257416B2
公开(公告)日：2022-02-22
申请号：US16848706
申请日：2020-04-14
Applicant: Samsung Display Co., Ltd.
Inventor： Anup P. Jose , Younghoon Song
IPC: G09G3/20
Abstract: A circuit. In some embodiments, the circuit includes: a drive circuit having an output and including: a pre-emphasis circuit; and an output stage connected to an output of the pre-emphasis circuit. The pre-emphasis circuit may be configured to generate, during a first interval of time, a pre-emphasized signal. The output stage may be configured to produce, at the output of the drive circuit, a constant signal based on the pre-emphasized signal during the first interval of time, and to disconnect the pre-emphasis circuit from the output of the drive circuit during a second interval of time, the second interval of time beginning at the end of the first interval of time.
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公开(公告)号：US11087656B2
公开(公告)日：2021-08-10
申请号：US16656447
申请日：2019-10-17
Applicant: Samsung Display Co., Ltd.
Inventor： Anup P. Jose , Amir Amirkhany , Mohamed Elzeftawi
Abstract: A system and method for sensing drive current in a pixel. In some embodiments, the system includes: a first pixel, a second pixel, a differential sensing circuit, a reference current source, and a control circuit. The differential sensing circuit may have a first input, a second input, and an output, the first input being connected to a node at which a reference current generated by the reference current source is subtracted from a first pixel current, the first pixel current including a current generated by the first pixel. The second input may be configured to receive a second pixel current, the second pixel current including a current generated by the second pixel. The output may be configured to produce an output signal based on a difference between a current received at the first input and a current received at the second input.
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公开(公告)号：US11004387B2
公开(公告)日：2021-05-11
申请号：US16283514
申请日：2019-02-22
Applicant: Samsung Display Co., Ltd.
Inventor： Anup P. Jose
IPC: G09G3/36 , G09G3/3233 , H03K19/21
Abstract: A device includes a segmented pull-up current source circuit including a first plurality of transistors, a segmented pull-down current source circuit including a second plurality of transistors, a comparator circuit configured to compare an output voltage level at the output of the device with a target voltage level and generate a comparator output at one of two output terminals of the comparator circuit, wherein the segmented pull-up current source circuit and the segmented pull-down current source circuit are connected to the two output terminals of the comparator circuit via one or more multiplexers, the first plurality of AND gate circuits and a second plurality of AND gate circuits; and a logic circuit connected to at least one output terminal of the comparator circuit and configured to control an operation of the segmented pull-up current source circuit and the segmented pull-down current source circuit based on the comparator output.
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公开(公告)号：US11870880B2
公开(公告)日：2024-01-09
申请号：US17714104
申请日：2022-04-05
Applicant: Samsung Display Co., Ltd.
Inventor： Younghoon Song , Anup P. Jose
CPC classification number: H04L7/0016 , H03L7/085 , H03L7/0807 , H03L7/099 , H03M1/66
Abstract: A digital clock data recovery circuit including: a first vote circuit connected at an output of a first deserializer and configured to generate an even up/down signal based on even deserialized signals from the first deserializer; a first digital to analog converter (DAC) connected at an output of the first vote circuit and configured to control a voltage and/or frequency of a voltage controlled oscillator (VCO) based on the even up/down signal from the first vote circuit; a second vote circuit connected at an output of a second deserializer and configured to generate an odd up/down signal based on odd deserialized signals from the second deserializer; and a second DAC connected at an output of the second vote circuit and configured to control the voltage and/or frequency of the VCO based on the odd up/down signal from the second vote circuit.
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Patent Agency Ranking
公开(公告)号：US20230246800A1
公开(公告)日：2023-08-03
申请号：US17714104
申请日：2022-04-05
Applicant: Samsung Display Co.,Ltd.
Inventor： Younghoon Song , Anup P. Jose
CPC classification number: H04L7/0016 , H03L7/0807 , H03L7/085 , H03M1/66 , H03L7/099
Abstract: A digital clock data recovery circuit including: a first vote circuit connected at an output of a first deserializer and configured to generate an even up/down signal based on even deserialized signals from the first deserializer; a first digital to analog converter (DAC) connected at an output of the first vote circuit and configured to control a voltage and/or frequency of a voltage controlled oscillator (VCO) based on the even up/down signal from the first vote circuit; a second vote circuit connected at an output of a second deserializer and configured to generate an odd up/down signal based on odd deserialized signals from the second deserializer; and a second DAC connected at an output of the second vote circuit and configured to control the voltage and/or frequency of the VCO based on the odd up/down signal from the second vote circuit.
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公开(公告)号：US10411593B1
公开(公告)日：2019-09-10
申请号：US16109645
申请日：2018-08-22
Applicant: Samsung Display Co., Ltd.
Inventor： Valentin Abramzon , Amir Amirkhany , Anup P. Jose
Abstract: A system and method for a decimated phase detector circuit includes a bang bang phase detector (BBFD), an UP rolling counter connected to an UP output of the BBFD, and a DOWN rolling counter connected to a DOWN output of the BBFD. A charge pump is connected to the UP rolling counter and the DOWN rolling counter and is configured to receive a decimated UP signal from the UP rolling counter and a decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage according to the received decimated UP signals and decimated DOWN signals.
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公开(公告)号：US20210049963A1
公开(公告)日：2021-02-18
申请号：US16657680
申请日：2019-10-18
Applicant: Samsung Display Co., Ltd.
Inventor： Amir Amirkhany , Anup P. Jose , Gaurav Malhotra , Younghoon Song , Mohamed Elzeftawi
IPC: G09G3/3258 , G09G3/20
Abstract: A system and method for estimating and using pixel compensation coefficients. In some embodiments, the method includes, during a first time interval: comparing a first pixel current for a pixel of the display with a first reference current, to obtain a first pixel current error signal, the first pixel current error signal being the sign of a difference between the first pixel current and the first reference current; and updating one or more compensation coefficients for the pixel, based on the first pixel current error signal.
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公开(公告)号：US20190273639A1
公开(公告)日：2019-09-05
申请号：US16058896
申请日：2018-08-08
Applicant: Samsung Display Co., Ltd.
Inventor： Anup P. Jose , Amir Amirkhany , Mohammad Hekmat
Abstract: A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.
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公开(公告)号：US10186208B2
公开(公告)日：2019-01-22
申请号：US15402136
申请日：2017-01-09
Applicant: Samsung Display Co., Ltd.
Inventor： Anup P. Jose , Amir Amirkhany
IPC: G09G3/32 , G09G3/36 , G09G3/3291 , H01L27/092 , H01L29/78
Abstract: A column driver includes: an output stage including: a first transistor and a second transistor coupled in series between an output high voltage source and an output low voltage source; and an output node between the first transistor and the second transistor, the first transistor and the second transistor being configured to control an output voltage of the output node in an output voltage range; a first operational amplifier having a first operating voltage range, an output of the first operational amplifier being connected to a gate electrode of the first transistor, the first operating voltage range being smaller than the output voltage range; a second operational amplifier having a second operating voltage range, an output of the second operational amplifier being connected to a gate electrode of the second transistor; and a feedback network coupled between the output node and non-inverting inputs of the first and second operational amplifiers.
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