公开(公告)号：US10700114B2

公开(公告)日：2020-06-30

申请号：US15737402

申请日：2017-04-11

Applicant: SONY CORPORATION

Inventor： Hideyuki Honda ,  Tetsuya Uchida ,  Toshifumi Wakano ,  Yusuke Tanaka ,  Yoshiharu Kudoh ,  Hirotoshi Nomura ,  Tomoyuki Hirano ,  Shinichi Yoshida ,  Yoichi Ueda ,  Kosuke Nakanishi

IPC: H01L27/146 ,  H01L21/76 ,  H04N5/365 ,  H04N5/378 ,  H04N5/376

Abstract: The present technology relates to a solid-state imaging element configured so that pixels can be more reliably separated, a method for manufacturing the solid-state imaging element, and an electronic apparatus. The solid-state imaging element includes a photoelectric converter, a first separator, and a second separator. The photoelectric converter is configured to perform photoelectric conversion of incident light. The first separator configured to separate the photoelectric converter is formed in a first trench formed from a first surface side. The second separator configured to separate the photoelectric converter is formed in a second trench formed from a second surface side facing a first surface. The present technology is applicable to an individual imaging element mounted on, e.g., a camera and configured to acquire an image of an object.

公开(公告)号：US20150340503A1

公开(公告)日：2015-11-26

申请号：US14719995

申请日：2015-05-22

Applicant: IMEC VZW ,  Sony Corporation

Inventor： Hideki Minari ,  Shinichi Yoshida ,  Geoffrey Pourtois ,  Matty Caymax ,  Eddy Simoen

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/762 ,  H01L21/3205 ,  H01L29/20 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02538 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/20 ,  H01L29/66522 ,  H01L29/7851

Abstract: A method of producing a III-V fin structure within a gap separating shallow trench isolation (STI) structures and exposing a semiconductor substrate is disclosed, the method comprising providing a semiconductor substrate, providing in the semiconductor substrate at least two identical STI structures separated by a gap exposing the semiconductor substrate, wherein said gap is bounded by said at least two identical STI structures, and, producing a III-V fin structure within said gap on the exposed semiconductor substrate, and providing a diffusion barrier at least in contact with each side wall of said at least two identical STI structures and with side walls of said III-V fin structure and wherein said semiconductor substrate is a Si substrate.

Abstract translation: 公开了在分离浅沟槽隔离（STI）结构和暴露半导体衬底的间隙内产生III-V鳍结构的方法，该方法包括提供半导体衬底，在半导体衬底中提供至少两个相同的STI结构， 暴露半导体衬底的间隙，其中所述间隙由所述至少两个相同的STI结构限定，并且在所述暴露的半导体衬底上的所述间隙内产生III-V鳍结构，并且提供至少与每个 所述至少两个相同的STI结构的侧壁和所述III-V鳍结构的侧壁，并且其中所述半导体衬底是Si衬底。

公开(公告)号：US09431519B2

公开(公告)日：2016-08-30

申请号：US14719995

申请日：2015-05-22

Applicant: IMEC VZW ,  Sony Corporation

Inventor： Hideki Minari ,  Shinichi Yoshida ,  Geoffrey Pourtois ,  Matty Caymax ,  Eddy Simoen

IPC: H01L27/088 ,  H01L21/336 ,  H01L29/66 ,  H01L29/20 ,  H01L29/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/762 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02538 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/20 ,  H01L29/66522 ,  H01L29/7851

Abstract: A method of producing a III-V fin structure within a gap separating shallow trench isolation (STI) structures and exposing a semiconductor substrate is disclosed, the method comprising providing a semiconductor substrate, providing in the semiconductor substrate at least two identical STI structures separated by a gap exposing the semiconductor substrate, wherein said gap is bounded by said at least two identical STI structures, and, producing a III-V fin structure within said gap on the exposed semiconductor substrate, and providing a diffusion barrier at least in contact with each side wall of said at least two identical STI structures and with side walls of said III-V fin structure and wherein said semiconductor substrate is a Si substrate.

Abstract translation: 公开了在分离浅沟槽隔离（STI）结构和暴露半导体衬底的间隙内产生III-V鳍结构的方法，该方法包括提供半导体衬底，在半导体衬底中提供至少两个相同的STI结构， 暴露半导体衬底的间隙，其中所述间隙由所述至少两个相同的STI结构界定，并且在所述暴露的半导体衬底上的所述间隙内产生III-V鳍结构，并且提供至少与每个 所述至少两个相同的STI结构的侧壁和所述III-V鳍结构的侧壁，并且其中所述半导体衬底是Si衬底。

公开(公告)号：US10580821B2

公开(公告)日：2020-03-03

申请号：US16064594

申请日：2016-12-27

Applicant: SONY CORPORATION

Inventor： Shinichi Yoshida

IPC: H01L27/146 ,  H01L31/0224 ,  H01L31/0304 ,  H01L31/18

Abstract: This light-receiving element includes a plurality of photoelectric conversion layers, each of which includes a compound semiconductor, and absorbs a wavelength in an infrared region to generate an electric charge, and an insulating film that is provided to surround each of the plurality of photoelectric conversion layers.