公开(公告)号：US20190214394A1

公开(公告)日：2019-07-11

申请号：US16351004

申请日：2019-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keun-hee BAI ,  Myeong-cheol KIM ,  Kwan-heum LEE ,  Do-hyoung KIM ,  Jin-wook LEE ,  Seung-mo HA ,  Dong-Hoon KHANG

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L27/1104 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.