公开(公告)号：US20240194752A1

公开(公告)日：2024-06-13

申请号：US18502352

申请日：2023-11-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Kyung YOU ,  Sang Koo KANG ,  Jun Chae LEE ,  Koung Min RYU ,  Woo Jin LEE

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate, an active pattern disposed on the substrate and extending in a first direction, gate electrodes covering the active pattern and extending in a second direction, a gate spacer disposed on a sidewall of each of the gate electrodes, a source/drain pattern disposed between adjacent ones of the gate electrodes, an etch stop film disposed along a sidewall of the gate spacer and a profile of the source/drain pattern, an interlayer insulating film disposed between the adjacent ones of the gate electrodes with a contact trench exposing the source/drain pattern defined therein, a liner film disposed on an outer sidewall of the contact trench, and a source/drain contact disposed on the liner film and filling the contact trench, in which the source/drain contact is connected to the source/drain pattern. At least a portion of the liner film may be disposed in the source/drain pattern.

公开(公告)号：US20240204107A1

公开(公告)日：2024-06-20

申请号：US18532230

申请日：2023-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Koo KANG ,  Woo Kyung YOU ,  Min Jae KANG ,  Koung Min RYU ,  Hoon Seok SEO ,  Woo Jin LEE ,  Jun Chae LEE

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/0886 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes: a substrate including an upper side and a lower side; first and second active patterns spaced apart from each other; a field insulating film covering side walls of the first and second active patterns; a power rail disposed adjacent to a first side wall of the second active pattern and between the first active pattern and the second active pattern; a power rail via disposed on the power rail and connected to the power rail; a semiconductor etching stop pattern disposed adjacent to a second side wall of the second active pattern; and a first semiconductor pattern disposed on the semiconductor etching stop pattern, wherein a lower surface of the semiconductor etching stop pattern is disposed on substantially a same plane as the lower side of the substrate, and wherein at least part of the first semiconductor pattern is disposed in the field insulating film.