公开(公告)号：US20160240553A1

公开(公告)日：2016-08-18

申请号：US15138873

申请日：2016-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNWOO LEE ,  SANGWOO LEE ,  CHANGWON LEE ,  JEONGGIL LEE

IPC: H01L27/115 ,  H01L23/535 ,  H01L29/49

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1159 ,  H01L29/4958 ,  H01L29/4966

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

公开(公告)号：US20220139832A1

公开(公告)日：2022-05-05

申请号：US17569774

申请日：2022-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： JEONGGIL LEE ,  SUKHOON KIM ,  SUNGMYONG PARK ,  CHANYANG LEE ,  HONYUN PARK

IPC: H01L23/528 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11582

Abstract: A wiring structure includes first to third metal patterns on a substrate. The first metal pattern extends in a second direction and has a first width in a third direction. The second metal pattern extends in the third direction to cross the first metal pattern and have a second width in the second direction. The third metal pattern is connected to the first and second metal patterns at an area where the first and second metal patterns cross each other, and has a substantially rectangular shape with concave portions in each quadrant. The third metal pattern has a third width defined as a minimum distance between opposite ones of the concave portions in a fourth direction having an acute angle to the second and third directions, which is less or equal to than a smaller of the first and second widths.

公开(公告)号：US20170309640A1

公开(公告)日：2017-10-26

申请号：US15644290

申请日：2017-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNWOO LEE ,  SANGWOO LEE ,  CHANGWON LEE ,  JEONGGIL LEE

IPC: H01L27/11582 ,  H01L29/49 ,  H01L27/11578 ,  H01L27/1157 ,  H01L23/535 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1159 ,  H01L29/4958 ,  H01L29/4966

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

公开(公告)号：US20180261499A1

公开(公告)日：2018-09-13

申请号：US15975003

申请日：2018-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGHO RHA ,  KYOUNG HEE NAM ,  JEONGGIL LEE ,  HYUNSEOK LIM ,  SEUNGJONG PARK ,  SEULGI BAE ,  JAEJIN LEE ,  KWANGTAE HWANG

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76882 ,  H01L23/53238

Abstract: A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection provided on a second region of the substrate. A width of the second metal interconnection is greater than a width of the first metal interconnection. The first metal interconnection includes a metal pattern. The second metal interconnection includes a lower metal pattern having a concave surface at its top, an upper metal pattern disposed on the concave surface at the top of the lower metal pattern, and a first barrier pattern interposed between the lower metal pattern and the upper metal pattern. The metal interconnections are formed by a damascene process including deposition, reflow, metal implantation, and planarization processes.

公开(公告)号：US20170170058A1

公开(公告)日：2017-06-15

申请号：US15332297

申请日：2016-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGHO RHA ,  KYOUNG HEE NAM ,  JEONGGIL LEE ,  HYUNSEOK LIM ,  SEUNGJONG PARK ,  SEULGI BAE ,  JAEJIN LEE ,  KWANGTAE HWANG

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76882 ,  H01L23/53238

Abstract: A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection provided on a second region of the substrate. A width of the second metal interconnection is greater than a width of the first metal interconnection. The first metal interconnection includes a metal pattern. The second metal interconnection includes a lower metal pattern having a concave surface at its top, an upper metal pattern disposed on the concave surface at the top of the lower metal pattern, and a first barrier pattern interposed between the lower metal pattern and the upper metal pattern. The metal interconnections are formed by a damascene process including deposition, reflow, metal implantation, and planarization processes.