公开(公告)号：US20160240553A1

公开(公告)日：2016-08-18

申请号：US15138873

申请日：2016-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNWOO LEE ,  SANGWOO LEE ,  CHANGWON LEE ,  JEONGGIL LEE

IPC: H01L27/115 ,  H01L23/535 ,  H01L29/49

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1159 ,  H01L29/4958 ,  H01L29/4966

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

公开(公告)号：US20170309640A1

公开(公告)日：2017-10-26

申请号：US15644290

申请日：2017-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNWOO LEE ,  SANGWOO LEE ,  CHANGWON LEE ,  JEONGGIL LEE

IPC: H01L27/11582 ,  H01L29/49 ,  H01L27/11578 ,  H01L27/1157 ,  H01L23/535 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1159 ,  H01L29/4958 ,  H01L29/4966

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

公开(公告)号：US20130059432A1

公开(公告)日：2013-03-07

申请号：US13667618

申请日：2012-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNWOO LEE ,  Sangwoo Lee ,  Changwon Lee ,  Jeonggil Lee

IPC: H01L21/28 ,  H01L21/20

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1159 ,  H01L29/4958 ,  H01L29/4966

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.