公开(公告)号：US20180261499A1

公开(公告)日：2018-09-13

申请号：US15975003

申请日：2018-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGHO RHA ,  KYOUNG HEE NAM ,  JEONGGIL LEE ,  HYUNSEOK LIM ,  SEUNGJONG PARK ,  SEULGI BAE ,  JAEJIN LEE ,  KWANGTAE HWANG

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76882 ,  H01L23/53238

Abstract: A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection provided on a second region of the substrate. A width of the second metal interconnection is greater than a width of the first metal interconnection. The first metal interconnection includes a metal pattern. The second metal interconnection includes a lower metal pattern having a concave surface at its top, an upper metal pattern disposed on the concave surface at the top of the lower metal pattern, and a first barrier pattern interposed between the lower metal pattern and the upper metal pattern. The metal interconnections are formed by a damascene process including deposition, reflow, metal implantation, and planarization processes.

公开(公告)号：US20170170058A1

公开(公告)日：2017-06-15

申请号：US15332297

申请日：2016-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGHO RHA ,  KYOUNG HEE NAM ,  JEONGGIL LEE ,  HYUNSEOK LIM ,  SEUNGJONG PARK ,  SEULGI BAE ,  JAEJIN LEE ,  KWANGTAE HWANG

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76882 ,  H01L23/53238

Abstract: A semiconductor device includes a substrate, a first metal interconnection provided on a first region of the substrate, and a second metal interconnection provided on a second region of the substrate. A width of the second metal interconnection is greater than a width of the first metal interconnection. The first metal interconnection includes a metal pattern. The second metal interconnection includes a lower metal pattern having a concave surface at its top, an upper metal pattern disposed on the concave surface at the top of the lower metal pattern, and a first barrier pattern interposed between the lower metal pattern and the upper metal pattern. The metal interconnections are formed by a damascene process including deposition, reflow, metal implantation, and planarization processes.