公开(公告)号：US20150062852A1

公开(公告)日：2015-03-05

申请号：US14278835

申请日：2014-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-Jae LEE ,  Jin-Young JUNG

IPC: H01L23/522 ,  H01L49/02 ,  H05K1/18 ,  H01L23/15

CPC classification number: H05K1/181 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/642 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/111 ,  H05K1/183 ,  H05K3/305 ,  H05K3/3442 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2203/0465 ,  H05K2203/048 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Semiconductor packages having through electrodes and methods for fabricating the same are provided. The method for fabricating a semiconductor package may comprise providing a package substrate including a core having a top surface and a bottom surface and a plurality of surface mount pads on the top surface of the core, providing a passive component on the package substrate between the surface mount pads, and forming an electrical connection that fills spaces between the surface mount pads and the passive component provided therebetween and electrically connects the passive component to the package substrate.

Abstract translation: 提供了具有通过电极的半导体封装及其制造方法。 用于制造半导体封装的方法可以包括提供包括具有顶表面和底表面的芯的封装衬底和在芯的顶表面上的多个表面安装焊盘，在封装衬底的表面之间提供无源部件 并且形成电连接，其填充表面安装焊盘和设置在其间的无源部件之间的空间，并将无源部件电连接到封装衬底。

公开(公告)号：US20210259122A1

公开(公告)日：2021-08-19

申请号：US17036294

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Jae LEE ,  Sang Sub SONG

IPC: H05K5/02

Abstract: An electric apparatus includes a substrate having a ground pattern on a top surface of the substrate; a conductive housing on the ground pattern and having an insertion space; a conductive connector disposed between the ground pattern and the conductive housing and connected to the ground pattern and the conductive housing, wherein the conductive housing is fixed to the substrate via the conductive connector; and a conductive cover coupled to the conductive housing, wherein the conductive cover is configured to move from a first position, at which the conductive cover externally opens the insertion space, to a second position, at which the conductive cover closes the insertion space.

公开(公告)号：US20190301016A1

公开(公告)日：2019-10-03

申请号：US16207967

申请日：2018-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SHIN-JAE KANG ,  Dong-Hoon HAN ,  Do-Hyung KIM ,  Kyung-Wook PARK ,  Kevin BAE ,  Sun-Soo LEE ,  In-Jae LEE ,  Jeon-II LEE ,  Chae-Mook LIM

IPC: C23C16/455 ,  C23C16/34 ,  H01L21/285 ,  H01L21/768

Abstract: In a layer deposition method, a substrate is loaded into a process chamber. A gas filling tank is charged with a gas to a predetermined charge pressure. The pressure of the gas is elevated to a pressure greater than the predetermined charge pressure. The gas is introduced into the process chamber.

公开(公告)号：US20180088865A1

公开(公告)日：2018-03-29

申请号：US15652811

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Jae LEE ,  Kwang-Soo KIM ,  Hyong-Woo YU

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/16 ,  G06K19/0712 ,  G06K19/07732 ,  G06K19/07743 ,  G11C7/1042 ,  G11C7/22 ,  G11C16/30 ,  G11C2207/2209

Abstract: A memory card includes first and second groups of terminals, at least one controller, and first and second nonvolatile memories. The first group of terminals are adjacent to an edge at an insertion side of a substrate and include a first power terminal to provide a first voltage. The second group of terminals is spaced farther apart from the edge at the insertion side than the first group of terminals and includes a second power terminal to provide a second voltage. The at least one memory controller is connected to the first and second groups of terminals, and the first and second nonvolatile memories are independently connected to the at least one controller. The at least one controller simultaneously accesses the first nonvolatile memory and the second nonvolatile memory when the first group of terminals and the second group of terminals are connected to an external host.

公开(公告)号：US20220392880A1

公开(公告)日：2022-12-08

申请号：US17671742

申请日：2022-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Jae LEE

IPC: H01L25/16 ,  H01L23/31 ,  H01R13/66 ,  H01L21/56

Abstract: A semiconductor package includes a package substrate, a semiconductor chip on the package substrate, the semiconductor chip including a logic chip and a memory stack structure on the logic chip, a connector and a connector terminal below the package substrate, a molding layer that covers the semiconductor chip, the molding layer having a recess region on a top surface of the molding layer, a housing that covers the molding layer, and an air gap on the semiconductor chip, the air gap being defined by the housing and the recess region of the molding layer, and the molding layer separating the air gap from the memory stack structure of the semiconductor chip.