公开(公告)号：US20240096995A1

公开(公告)日：2024-03-21

申请号：US18231841

申请日：2023-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomjin PARK ,  Myunggil KANG ,  Dongwon KIM ,  Younggwon KIM ,  Hyumin YOO ,  Soojin JEONG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device, may include an active region extending in a first direction; a plurality of channel layers on the active region to be spaced apart from each other; a gate structure, surrounding the plurality of channel layers, respectively; and source/drain regions on the active region on at least one side of the gate structure, and contacting the plurality of channel layers, wherein the gate structure may include an upper portion on an uppermost channel layer among the plurality of channel layers and lower portions between each of the plurality of channel layers in a region vertically overlapping the plurality of channel layers, wherein a width of each of the plurality of channel layers in the first direction may be less than a width of lower portions of the gate structure, adjacent to the respective channel layers among the lower portions of the gate structure in the first direction.

公开(公告)号：US20240355883A1

公开(公告)日：2024-10-24

申请号：US18385537

申请日：2023-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyumin YOO ,  Myung Gil KANG ,  Dongwon KIM ,  Jongsu KIM ,  Beomjin PARK ,  Byeonghee SON

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0847 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/0653

Abstract: A semiconductor device includes a substrate including an active pattern; a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns, which are stacked to be spaced apart from each other; a source/drain pattern connected to the plurality of semiconductor patterns; a gate electrode on the plurality of semiconductor patterns; and a blocking layer between the source/drain pattern and the active pattern, wherein the source/drain pattern includes a protruding side surface protruding toward the semiconductor patterns, the blocking layer includes silicon-germanium (SiGe), and a germanium concentration of the blocking layer is higher than a germanium concentration of the source/drain pattern.

公开(公告)号：US20240178293A1

公开(公告)日：2024-05-30

申请号：US18228824

申请日：2023-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyumin YOO ,  Beomjin PARK ,  Myung Gil KANG ,  Dongwon KIM ,  Younggwon KIM

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/7848

Abstract: Disclosed is a semiconductor device comprising a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns spaced apart from and vertically stacked on each other, a source/drain pattern connected to the semiconductor patterns having a p-type, a gate electrode on the semiconductor patterns and including inner electrodes between neighboring semiconductor patterns and an outer electrode on an uppermost semiconductor pattern, and a gate dielectric layer between the gate electrode and the semiconductor patterns and including an inner gate dielectric layer adjacent to the inner electrode and an outer gate dielectric layer that extends from bottom to lateral surfaces of the outer electrode. The outer electrode and the outer gate dielectric layer have an inverted T shape.