公开(公告)号：US20150236089A1

公开(公告)日：2015-08-20

申请号：US14706329

申请日：2015-05-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuaki KAGOTOSHI ,  Koichi ARAI ,  Natsuki YOKOYAMA ,  Haruka SHIMIZU

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/808

CPC classification number: H01L29/0619 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66068 ,  H01L29/66893 ,  H01L29/8083

Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n−-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n−-type drift layer with a silicon oxide film formed on the n−-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n−-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n−-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

Abstract translation: 结型场效应晶体管的制造方法包括以下步骤：（a）在n +型SiC衬底上形成的n型漂移层的表面上形成n +型源极层; （b）通过用形成在用作掩模的n型漂移层上的氧化硅膜蚀刻n型漂移层的表面，形成以预定间隔设置的多个浅沟槽; （c）通过使用垂直离子注入方法通过用氮掺杂每个浅沟槽下方的n型漂移层来形成n型计数器掺杂层; （d）在氧化硅膜和浅沟槽的每个侧壁上形成侧壁间隔物; 和（e）通过使用垂直离子注入法，通过用铝掺杂每个浅沟槽下的n型漂移层来形成p型栅极层。

公开(公告)号：US20130334542A1

公开(公告)日：2013-12-19

申请号：US13970586

申请日：2013-08-19

Applicant: Renesas Electronics Corporation

Inventor： Koichi ARAI ,  Yasuaki KAGOTOSHI ,  Nobuo MACHIDA ,  Natsuki YOKOYAMA ,  Haruka SHIMIZU

IPC: H01L29/36

CPC classification number: H01L29/36 ,  H01L29/045 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66909 ,  H01L29/8083

Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

公开(公告)号：US20150041829A1

公开(公告)日：2015-02-12

申请号：US14495303

申请日：2014-09-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Haruka SHIMIZU ,  Natsuki YOKOYAMA

IPC: H01L27/06 ,  H01L29/16 ,  H01L29/808

CPC classification number: H01L27/0629 ,  H01L21/8213 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1608 ,  H01L29/66909 ,  H01L29/8083 ,  H01L29/868 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.

Abstract translation: 常闭型碳化硅结FET由于其特性的劣化而具有栅极不易使用的问题。 出现此问题的原因是为了实现常关，栅极电压应在0V关断，同时将导通状态栅极电压抑制在约2.5V，以防止电流通过pn 门和源之间的连接。 因此，从阈值电压到导通状态栅极电压的范围仅为约1V至2V，并且难以控制栅极电压。 在本发明中提供的是通过将常闭型碳化硅结FET的栅极耦合到具有等于或稍小于结FET的栅极电容的电容的元件而获得的电子电路器件。

公开(公告)号：US20140284625A1

公开(公告)日：2014-09-25

申请号：US14220447

申请日：2014-03-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuaki KAGOTOSHI ,  Koichi ARAI ,  Natsuki YOKOYAMA ,  Haruka SHIMIZU

IPC: H01L29/808 ,  H01L29/66

CPC classification number: H01L29/0619 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66068 ,  H01L29/66893 ,  H01L29/8083

Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n−-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n−-type drift layer with a silicon oxide film formed on the n−-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n−-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n−-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

Abstract translation: 结型场效应晶体管的制造方法包括以下步骤：（a）在n +型SiC衬底上形成的n型漂移层的表面上形成n +型源极层; （b）通过用形成在用作掩模的n型漂移层上的氧化硅膜蚀刻n型漂移层的表面，形成以预定间隔设置的多个浅沟槽; （c）通过使用垂直离子注入方法通过用氮掺杂每个浅沟槽下方的n型漂移层来形成n型计数器掺杂层; （d）在氧化硅膜和浅沟槽的每个侧壁上形成侧壁间隔物; 和（e）通过使用垂直离子注入法，通过用铝掺杂每个浅沟槽下的n型漂移层来形成p型栅极层。