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公开(公告)号：US11373267B2
公开(公告)日：2022-06-28
申请号：US16673564
申请日：2019-11-04
Applicant: QUALCOMM Incorporated
Inventor： Tao Wang , Shambhoo Khandelwal , Andrew Evan Gruber , Shangmei Yu , Jing Gao , Junmei Shao , Thomas Edwin Frisinger , Rick Hammerstone
Abstract: The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure can determine a portion of a display area, where the portion of the display area is determined based on display content of the display area. Further, aspects of the present disclosure can communicate display information corresponding to the determined portion of the display area. Additionally, aspects of the present disclosure can update the display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also communicate the updated display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also render at least some display content of the display area corresponding to the determined portion of the display area. In some aspects, the updated display information can be based on the rendered display content of the display area.
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公开(公告)号：US11342961B1
公开(公告)日：2022-05-24
申请号：US17141025
申请日：2021-01-04
Applicant: QUALCOMM Incorporated
Inventor： Marvin Leroy Vis , Julio Zegarra , Thanh Duong , Thomas Funk , Erez Avigdor Falkenstein , Larry Flowers , Andrew Lejman , Joshua Britton , Tao Wang , Ali Morshedi
Abstract: Methods and apparatus are disclosed for near field radio-frequency (RF) testing of devices, particularly user equipment (UEs) capable of millimeter-wave (mmWave) transmissions. An exemplary test apparatus is described that uses a transducer to facilitate near field over-the-air testing of UEs in the mmWave transmission band. The transducer may be an orthomode transducer and may include a dual-polarity port positioned in the reactive near field of an antenna of a device under test (DUT). For UE signal transmission tests, the orthomode transducer splits test signals received from the antenna of the DUT via the dual-polarity port into a pair of single-polarity RF signals. The single-polarity RF signals are separately fed through a pair of waveguide-to-coaxial adaptors into separate coaxial cables, which feed coaxial transmission versions of the single-polarity RF signals to test equipment for analysis. UE signal reception tests are also described that utilize the same or different orthomode transducer.
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公开(公告)号：US10331526B2
公开(公告)日：2019-06-25
申请号：US15170742
申请日：2016-06-01
Applicant: QUALCOMM Incorporated
Inventor： Edwin Jose , Tao Wang
Abstract: Some aspects of the disclosure include a self-refresh entry sequence for a memory, such as a DRAM, that may be used to avoid a frequency mismatch between a system processor and a system memory. The self-refresh entry sequence may signal the memory to reset the frequency set point state and default to the power-up state upon a self-refresh process exit. In another aspect, a new mode register may be used to indicate that the frequency set point needs to be reset after the next self-refresh entry command. In this aspect, the processor will execute a mode register write command followed by a self-refresh entry in response to the occurrence of a crash event. Then, the memory will reset to the default frequency set point by the end of self-refresh entry execution.
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公开(公告)号：US09805495B2
公开(公告)日：2017-10-31
申请号：US15054717
申请日：2016-02-26
Applicant: QUALCOMM Incorporated
Inventor： Juraj Obert , Tao Wang , Vineet Goel
CPC classification number: G06T15/005 , G06T15/06 , G06T2200/28 , G06T2210/21
Abstract: A render output unit running on at least one processor may receive a source pixel value to be written to a pixel location in a render target, wherein the source pixel value is associated with a source node in a hierarchical structure. The render output unit may receive a destination pixel value of the pixel location in the render target, wherein the destination pixel value is associated with a destination node in the hierarchical structure. The render output unit may determine a lowest common ancestor node of the source node and the destination node in the hierarchical structure. The render output unit may output a resulting pixel value associated with the lowest common ancestor node of the source node and the destination node to the pixel location in the render target.
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公开(公告)号：US20170024926A1
公开(公告)日：2017-01-26
申请号：US14805088
申请日：2015-07-21
Applicant: QUALCOMM Incorporated
Inventor： Nagarjuna Duvvuru , Tao Wang , Jian Liang , Chunlin Wang
CPC classification number: G06T15/40 , G06T11/40 , G06T15/005 , G06T2200/04 , G06T2200/12 , G06T2200/28
Abstract: A graphics processing unit (GPU) may include a triangle setup engine (TSE) configured to determine coordinates of a triangle, rotate coordinates of the triangle based on an angle. To rotate the coordinates, the TSE generates coordinates of the triangle in a rotated domain, and determines coordinates of a bounding box in the rotated domain based on the coordinates of the triangle in the rotated domain. The TSE determines a first plurality of parallel scanlines in the rotated domain, and a second plurality of parallel scanlines in the rotated domain. The first and second pluralities of scanlines are perpendicular. The TSE determines whether the bounding box coordinates are located within two adjacent scanlines. If the bounding box coordinates are located within the two adjacent scanlines, the TSE removes the triangle from the scene.
Abstract translation: 图形处理单元（GPU）可以包括被配置为确定三角形的坐标的三角形设置引擎（TSE），基于角度旋转三角形的坐标。 为了旋转坐标，TSE在旋转的域中生成三角形的坐标，并根据旋转域中的三角形的坐标确定旋转域中边界框的坐标。 TSE确定旋转域中的第一多个平行扫描线和旋转域中的第二多个并行扫描线。 第一和第二扫描线是垂直的。 TSE确定边界框坐标是否位于两个相邻的扫描线之内。 如果边界框坐标位于两个相邻的扫描线内，则TSE会从场景中删除三角形。
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Patent Agency Ranking
公开(公告)号：US20150379663A1
公开(公告)日：2015-12-31
申请号：US14316275
申请日：2014-06-26
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber , Tao Wang , Chunhui Mei , Gang Zhong , Feng Ge
IPC: G06T1/20
CPC classification number: G06T1/20 , G06T11/40 , G06T15/005 , G09G5/363 , G09G2340/0407 , G09G2360/122
Abstract: In an example, a method for rendering graphics data includes rendering pixels of a first bin of a plurality of bins, wherein the pixels of the first bin are associated with a first portion of an image, and rendering, to the first bin, one or more pixels that are located outside the first portion of the image and associated with a second, different bin of the plurality of bins. The method also includes rendering the one or more pixels associated with the second bin to the second bin, such that the one or more pixels are rendered to both the first bin and the second bin.
Abstract translation: 在一个示例中，用于渲染图形数据的方法包括渲染多个箱的第一仓的像素，其中第一仓的像素与图像的第一部分相关联，并且向第一仓中呈现一个或 更多的像素位于图像的第一部分之外并且与多个箱的第二不同仓相关联。 该方法还包括将与第二仓相关联的一个或多个像素渲染到第二仓，使得一个或多个像素被渲染到第一仓和第二仓。
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公开(公告)号：US12079897B2
公开(公告)日：2024-09-03
申请号：US17935031
申请日：2022-09-23
Applicant: QUALCOMM Incorporated
Inventor： Kalyan Kumar Bhiravabhatla , Andrew Evan Gruber , Rahul Sunil Kukreja , Vishwanath Shashikant Nikam , Tao Wang , Jian Liang
CPC classification number: G06T1/20 , G06T1/60 , G06T15/005 , G06T15/405
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for improving visibility generation in tile-based GPU architectures. A graphics processor may perform a first binning pass associated with visibility information for each of a plurality of primitives in at least one frame. The visibility information for each of the plurality of primitives may correspond to a visible indication or an invisible indication. The graphics processor may update a depth buffer based on the visibility information for all of the plurality of primitives in the at least one frame. The graphics processor may perform a second binning pass for each of the visible set of primitives based on the updated depth buffer. The graphics processor may store at least one of the updated visibility information or updated position data for all primitives in the visible set of primitives from the second binning pass.
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公开(公告)号：US20210383545A1
公开(公告)日：2021-12-09
申请号：US16892096
申请日：2020-06-03
Applicant: QUALCOMM Incorporated
Inventor： Jian Liang , Andrew Evan Gruber , Tao Wang , Srihari Babu Alla , Kalyan Kumar Bhiravabhatla , Jonnala Gadda Nagendra Kumar , William Licea-Kane , Fredrick Alan Hickman
Abstract: Methods, systems, and devices for graphics processing are described. A device may receive an image including a set of pixels. The device may render a first subset of pixels in each bin of a set of bins during a first rendering pass, and defer rendering a second subset of pixels and a third subset of pixels in each bin of the set of bins during the first rendering pass. The second subset of pixels may include edge pixels and the third subset of pixels may be between the first subset of pixels and the second subset of pixels. The device may render the second subset of pixels and the third subset of pixels in each bin of the set of bins during a second rendering pass based on rendering the first subset of pixels. The device may then output the image based on the first and second rendering pass.
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公开(公告)号：US20200273142A1
公开(公告)日：2020-08-27
申请号：US16282003
申请日：2019-02-21
Applicant: QUALCOMM Incorporated
Inventor： Shambhoo Khandelwal , Tao Wang , Shangmei Yu , Jing Gao , Jian Liang , Andrew Evan Gruber , Chun Yu
Abstract: The described techniques provide for bin-based rendering where the scene geometry in a frame is subdivided into bins or tiles, and bins are resolved concurrently with the rendering of a next bin. For example, a graphics processing unit (GPU) may process an entire image and sort transactions (e.g., rasterized primitives, such as triangles) into bins. For the rendering of each transaction, a device may identify a memory address of a memory block (e.g., a unit or portion of internal GPU memory (GMEM)) the transaction will be written (i.e., rendered) to. The device may thus prepare the memory block for rendering (e.g., by performing a resolve operation, a clear operation, or an unresolve operation on the memory block), such that the memory block is prepared prior to rendering of the particular transaction. As such, transactions of a bin may be resolved concurrently with rendering of transactions of a next bin.
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公开(公告)号：US10445902B2
公开(公告)日：2019-10-15
申请号：US15377801
申请日：2016-12-13
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber , Serag GadelRab , Zhenbiao Ma , Meghal Varia , Tao Wang , Tom Longo , Mark Sternberg , Paul Chow
Abstract: Techniques are described in which a device is configured to retrieve a metadata buffer for rendering a sub-frame of a set of sub-frames for a frame. A data block of a data buffer is configured to store image data for rendering the sub-frame. In response to determining, based on the metadata buffer for rendering the sub-frame, that the sub-frame includes a color pattern, fixed color value, or combination thereof, the device refrains from retrieving the image data from the data block of the data buffer and determines the image data for rendering the sub-frame based on the metadata buffer.
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