公开(公告)号：US20170286314A1

公开(公告)日：2017-10-05

申请号：US15084886

申请日：2016-03-30

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Shaul Yohai Yifrach ,  Thomas Zeng

IPC: G06F12/10 ,  G06F3/06

CPC classification number: G06F12/1027 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/28 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/683 ,  Y02D10/13

Abstract: Hardware-based translation lookaside buffer (TLB) invalidation techniques are disclosed. A host system is configured to exchange data with a peripheral component interconnect express (PCIe) endpoint (EP). A memory management unit (MMU), which is a hardware element, is included in the host system to provide address translation according to at least one TLB. In one aspect, the MMU is configured to invalidate the at least one TLB in response to receiving at least one TLB invalidation command from the PCIe EP. In another aspect, the PCIe EP is configured to determine that the at least one TLB needs to be invalidated and provide the TLB invalidation command to invalidate the at least one TLB. By implementing hardware-based TLB invalidation in the host system, it is possible to reduce TLB invalidation delay, thus leading to increased data throughput, reduced power consumption, and improved user experience.

公开(公告)号：US20150033234A1

公开(公告)日：2015-01-29

申请号：US14338235

申请日：2014-07-22

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Itai Lanel ,  Maya Haim (Erez)

IPC: G06F9/52

CPC classification number: G06F9/522 ,  G06F9/4843

Abstract: A host controller is provided that unilaterally supports queue barrier functionality. The host controller may receive a first task marked with a queue barrier indicator. As a result, the host controller stalls transmission of the first task to a target device. Additionally, the host controller also stalls transmission of any task, occurring after the first task, to the target device. The host controller only sends the first task to the target device once an indication is received from the target device that all previously sent tasks have been processed. The host controller only sends any task, occurring after the first task, to the target device once an indication is received from the target device that the first task has been processed.

Abstract translation: 提供了一个主机控制器，其单方面支持队列阻挡功能。 主机控制器可以接收标记有队列障碍指示符的第一任务。 结果，主机控制器将第一任务的传输停止到目标设备。 此外，主机控制器还将发生在第一任务之后的任何任务的传输停止到目标设备。 一旦从目标设备接收到所有先前发送的任务已被处理的指示，主机控制器才将第一个任务发送到目标设备。 一旦从目标设备接收到已经处理了第一个任务的指示，主机控制器才将发生在第一个任务之后的任何任务发送到目标设备。

公开(公告)号：US09632953B2

公开(公告)日：2017-04-25

申请号：US14728343

申请日：2015-06-02

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Dolev Raviv ,  David Teb

IPC: G06F12/00 ,  G06F13/16 ,  G06F3/06

CPC classification number: G06F13/16 ,  G06F3/06 ,  G06F3/061 ,  G06F3/0664 ,  G06F3/0688 ,  G11C7/00

Abstract: An input/output virtualization (IOY) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is coupled to input/output (I/O) clients via corresponding client register interfaces (CRIs), and is also coupled to a flash-memory-based storage device. The IOV-HC comprises transfer request list (TRL) slot offset registers indicating slots of a shared TRL that are assigned as base slots to each of the CRIs. The IOV-HC further comprises TRL slot count registers indicating how many slots of the shared TRL are assigned to each of the CRIs. When a transfer request (TR) directed to the flash-memory-based storage device is received from a CRI, the IOV-HC is configured to map the TR to a slot of the shared TRL based on a TRL slot offset register and a TRL slot count register of the plurality of TRL slot count registers corresponding to the CRI.

公开(公告)号：US20170068460A1

公开(公告)日：2017-03-09

申请号：US15254986

申请日：2016-09-01

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk SHIN ,  Jung Pill KIM ,  Assaf Shacham

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0608 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0625 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0665 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0688

Abstract: Aspects disclosed in the detailed description include hardware accelerated storage compression. In one aspect, prior to writing an uncompressed data block to the storage device, a hardware compression accelerator provided in a storage controller compresses the uncompressed data blocks individually into a compressed data block and allocates the compressed data block to a storage data block in the storage device. The hardware compression accelerator then generates a modified logical block address (LBA) to link the uncompressed data block to the compressed data blocks. In another aspect, the hardware compression accelerator locates a compressed data block based on a corresponding modified LBA and decompresses the compressed data block into an uncompressed data block. By performing hardware accelerated storage compression in the storage controller, it is possible to reduce processing overhead associated with traditional software-based compression systems and improve compression control over traditional storage device driven compression systems.

Abstract translation: 在详细描述中公开的方面包括硬件加速存储压缩。 一方面，在将未压缩的数据块写入到存储装置之前，设置在存储控制器中的硬件压缩加速器将未压缩数据块分别压缩为压缩数据块，并将压缩数据块分配给存储器中的存储数据块 设备。 硬件压缩加速器然后生成修改的逻辑块地址（LBA），以将未压缩的数据块链接到压缩的数据块。 在另一方面，硬件压缩加速器基于对应的修改的LBA定位压缩数据块，并将压缩数据块解压缩为未压缩的数据块。 通过在存储控制器中执行硬件加速存储压缩，可以减少与传统的基于软件的压缩系统相关联的处理开销，并改进对传统存储设备驱动的压缩系统的压缩控制。

公开(公告)号：US20150347016A1

公开(公告)日：2015-12-03

申请号：US14728343

申请日：2015-06-02

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Dolev Raviv ,  David Teb

IPC: G06F3/06

CPC classification number: G06F13/16 ,  G06F3/06 ,  G06F3/061 ,  G06F3/0664 ,  G06F3/0688 ,  G11C7/00

Abstract: An input/output virtualization (IOY) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is coupled to input/output (I/O) clients via corresponding client register interfaces (CRIs), and is also coupled to a flash-memory-based storage device. The IOV-HC comprises transfer request list (TRL) slot offset registers indicating slots of a shared TRL that are assigned as base slots to each of the CRIs. The IOV-HC further comprises TRL slot count registers indicating how many slots of the shared TRL are assigned to each of the CRIs. When a transfer request (TR) directed to the flash-memory-based storage device is received from a CRI, the IOV-HC is configured to map the TR to a slot of the shared TRL based on a TRL slot offset register and a TRL slot count register of the plurality of TRL slot count registers corresponding to the CRI.

Abstract translation: 公开了一种基于闪存存储器的存储设备的输入/输出虚拟化（IOY）主机控制器（HC）（IOV-HC）。 在一个方面，IOV-HC通过相应的客户端寄存器接口（CRI）耦合到输入/输出（I / O）客户端，并且还耦合到基于闪存存储器的存储设备。 IOV-HC包括指示被分配为每个CRI的基准时隙的共享TRL的时隙的传送请求列表（TRL）时隙偏移量寄存器。 IOV-HC还包括TRL时隙计数寄存器，其指示共享TRL的多少时隙被分配给每个CRI。 当从CRI接收到指向基于闪速存储器的存储设备的传送请求（TR）时，IOV-HC被配置为基于TRL时隙偏移寄存器和TRL将TR映射到共享TRL的时隙 对应于CRI的多个TRL时隙计数寄存器的时隙计数寄存器。

公开(公告)号：US20150143022A1

公开(公告)日：2015-05-21

申请号：US14080852

申请日：2013-11-15

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Amit Gil

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0238 ,  G06F13/4068 ,  G06F2212/7207

Abstract: Removable memory card discrimination systems and methods are disclosed. In particular, exemplary embodiments discriminate between secure digital (SD) cards and other removable memory cards that comply with the SD form factor, but support the Universal Flash Storage (UFS) protocol. That is, a host may have a receptacle that supports the SD card form factor and is configured to receive a device. In use, a removable memory card is inserted into the receptacle and, using an SD compliant interrogation signal, the host interrogates a common area on the card so inserted. The common area includes information related to capability descriptors of the card. An SD compliant card will respond with information such as capability descriptors about the SD protocol capabilities, while a UFS compliant card will respond with an indication that the card is UFS compliant. The host may then restart the communication with the card using the UFS protocol.

Abstract translation: 公开了可移动存储卡鉴别系统和方法。 特别地，示例性实施例区分安全数字（SD）卡和符合SD外形尺寸但支持通用闪存存储（UFS）协议的其他可移动存储卡。 也就是说，主机可以具有支持SD卡形状因子的插座，并且被配置为接收设备。 在使用中，将可移动存储卡插入插座中，并且使用SD兼容询问信号，主机询问插入的卡上的公共区域。 公共区域包括与卡的能力描述符相关的信息。 SD兼容卡将响应诸如关于SD协议能力的能力描述符的信息，而符合UFS的卡将响应该卡符合UFS的指示。 然后，主机可以使用UFS协议重新启动与该卡的通信。

公开(公告)号：US20150074338A1

公开(公告)日：2015-03-12

申请号：US14467404

申请日：2014-08-25

Applicant: QUALCOMM Incorporated

Inventor： Dolev Raviv ,  Tatyana Brokhman ,  Maya Haim ,  Assaf Shacham

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0679 ,  G06F13/385 ,  G06F2206/1014

Abstract: Ascertaining command completion in flash memories is disclosed. An exemplary aspect includes eliminating the software lock and the outstanding requests variable and replacing them with a transfer request completion register. The transfer request completion register may be mapped to the universal flash storage (UFS) Transfer Protocol (UTP) Transfer Request List (UTRL) slots. The controller of the host—a hardware component—may set the bit in the transfer request completion register on transfer request completion at the same time the doorbell register is cleared. After this bit has been read, the bit in the transfer request completion register is cleared.

Abstract translation: 公开闪存中的确定命令完成。 示例性方面包括消除软件锁定和未完成的请求变量并用传送请求完成寄存器替换它们。 转移请求完成寄存器可以映射到通用闪存存储（UFS）传输协议（UTP）传输请求列表（UTRL）槽。 主机的控制器 - 硬件组件 - 可以在转移请求完成时将门铃寄存器清零的同时设置在传送请求完成寄存器中的位。 读取该位后，转移请求完成寄存器中的位将被清零。

公开(公告)号：US10114787B2

公开(公告)日：2018-10-30

申请号：US14609488

申请日：2015-01-30

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Yossi Amon ,  Nir Gerber ,  Assaf Shacham

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40 ,  H04L29/12

Abstract: Device identification generation in electronic devices to allow external control, such as selection or reprogramming, of device identification for bus communications identification, is disclosed. In this manner, device identifications of electronic devices coupled to a common communications bus in a system can be selected or reprogrammed to ensure they are unique to avoid bus communications collisions. In certain aspects, to select or reprogram a device identification in an electronic device, an external source can be electrically coupled to the electronic device. The external source closes a circuit with a device identification generation circuit in the electronic device. The closed circuit provides a desired electrical characteristic detectable by the device identification generation circuit. The device identification generation circuit is configured to generate a device identification as a function of the detected electrical characteristics of the closed circuit from the external source.

公开(公告)号：US09690720B2

公开(公告)日：2017-06-27

申请号：US14728400

申请日：2015-06-02

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Maya Haim ,  Lee Susman ,  David Teb

IPC: G06F12/00 ,  G06F13/16 ,  G06F3/06

CPC classification number: G06F13/1642 ,  G06F3/06 ,  G06F3/061 ,  G06F3/0664 ,  G06F3/0688 ,  G06F13/16

Abstract: Command trapping in an input/output virtualization (IOV) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is configured to receive a request from a client register interface (CRI) of one of multiple input/output (I/O) clients. The IOV-HC inspects a content of the request prior to the request being passed to a transport protocol engine. Based on the content, the IOV-HC determines whether the request should be further processed or should be trapped. If the IOV-HC determines that the request should be trapped, the IOV-HC traps the request using a request trap. In some aspects, the IOV-HC generates an interrupt to a virtual machine manager (VMM) to notify the VMM that the request was trapped. In some aspects, the IOV-HC provides a response generation circuit to receive instructions from the VMM to generate a response to the CRI from which the trapped request originated.

公开(公告)号：US09519440B2

公开(公告)日：2016-12-13

申请号：US14478032

申请日：2014-09-05

Applicant: QUALCOMM Incorporated

Inventor： Assaf Shacham ,  Tom Yahalom ,  Aviad Zacks-Shtrauss

IPC: G06F3/00 ,  G06F3/06 ,  G06F13/42

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679 ,  G06F13/4243 ,  G06F2003/0697 ,  G06F2206/1014

Abstract: Providing command queuing in embedded memories is provided. In particular, aspects disclosed herein relate to a process through which a status of the queue is communicated to a host from a device. Aspects of the present disclosure use the command structure of the embedded Multi-Media Card (eMMC) standard, such that the host may determine a state of the queue in the device proximate a known end of an in-progress data transfer. In this manner, the host can select a task to commence after completion of a current data transfer while the current data transfer is still ongoing.

Abstract translation: 提供了嵌入式存储器中的命令排队。 特别地，本文公开的方面涉及将队列的状态从设备传送到主机的过程。 本公开的方面使用嵌入式多媒体卡（eMMC）标准的命令结构，使得主机可以在接近于正在进行的数据传输的已知结束的情况下确定设备中的队列的状态。 以这种方式，当当前的数据传送仍在进行时，主机可以选择完成当前数据传输之后开始的任务。