公开(公告)号：US09524264B2

公开(公告)日：2016-12-20

申请号：US14316026

申请日：2014-06-26

Applicant: QUALCOMM Incorporated

Inventor： Yossi Amon ,  David Asher Friedman ,  Ben Levin ,  Sharon Graif

IPC: G06F13/36 ,  G06F13/42 ,  G06F13/364

CPC classification number: G06F13/4226 ,  G06F13/364 ,  G06F13/4291

Abstract: Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media are disclosed. In one aspect, a method for generating combined bus clock signals comprises detecting a start event by each master device of multiple master devices communicatively coupled to a shared clock line of a shared bus. Each master device samples a plurality of shared clock line values of the shared clock line at a corresponding plurality of transitions of a reference clock signal for the master device. Each master device determines whether the plurality of shared clock line values is identical. If the shared clock line values are identical, each master device drives a shared clock line drive value inverse to the plurality of shared clock line values to the shared clock line at a next transition of the reference clock signal for the master device.

Abstract translation: 公开了在共享总线系统中使用异步主设备参考时钟生成组合总线时钟信号，以及相关方法，设备和计算机可读介质。 一方面，一种用于产生组合总线时钟信号的方法包括：通过通信耦合到共享总线的共享时钟线的多个主设备的每个主设备检测起始事件。 每个主设备在主设备的参考时钟信号的相应多个转换处对共享时钟线的多个共享时钟线值进行采样。 每个主设备确定多个共享时钟线值是否相同。 如果共享时钟线路值相同，则在主设备的参考时钟信号的下一个转换处，每个主设备将共享时钟线驱动值与多个共享时钟线路值相反地驱动到共享时钟线路。

公开(公告)号：US20180260357A1

公开(公告)日：2018-09-13

申请号：US15453678

申请日：2017-03-08

Applicant: QUALCOMM Incorporated

Inventor： Yossi Amon ,  Lior Amarilio ,  Ofer Rosenberg

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/404 ,  G06F2213/0016

Abstract: Systems, methods, and apparatus are described that enable an I3C master device to support I2C clock stretch used by I2C devices connected to an I3C bus. A method performed at a master device includes enabling a line driver to drive a clock wire of the serial bus in accordance with a clock signal and when the master device is configured for a first mode of operation, enabling the line driver to drive the clock wire to a first voltage level when the clock signal is in a first signaling state and when the master device is configured for a second mode of operation, and disabling the line driver when the clock signal is in a second signaling state in the second mode of operation. A resistor pulls the clock wire to a second voltage level when the clock signal is in the second signaling state.

公开(公告)号：US20150220475A1

公开(公告)日：2015-08-06

申请号：US14609488

申请日：2015-01-30

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Yossi Amon ,  Nir Gerber ,  Assaf Shacham

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/364 ,  G06F13/409 ,  G06F13/4282 ,  G06F13/4291 ,  H04L61/2038 ,  H04L61/2046 ,  H04L61/2092 ,  H04L61/3005

Abstract: Device identification generation in electronic devices to allow external control, such as selection or reprogramming, of device identification for bus communications identification, is disclosed. In this manner, device identifications of electronic devices coupled to a common communications bus in a system can be selected or reprogrammed to ensure they are unique to avoid bus communications collisions. In certain aspects, to select or reprogram a device identification in an electronic device, an external source can be electrically coupled to the electronic device. The external source closes a circuit with a device identification generation circuit in the electronic device. The closed circuit provides a desired electrical characteristic detectable by the device identification generation circuit. The device identification generation circuit is configured to generate a device identification as a function of the detected electrical characteristics of the closed circuit from the external source.

Abstract translation: 公开了用于允许外部控制（例如选择或重新编程）用于总线通信识别的设备标识的电子设备中的设备识别生成。 以这种方式，可以选择或重新编程耦合到系统中的公共通信总线的电子设备的设备标识，以确保它们是唯一的，以避免总线通信冲突。 在某些方面，为了在电子设备中选择或重新编程设备识别，外部源可以电耦合到电子设备。 外部源在电子设备中用设备识别生成电路闭合电路。 封闭电路提供了可由设备识别生成电路检测的期望的电特性。 设备识别生成电路被配置为根据检测到的来自外部源的闭路电气特性产生设备标识。

公开(公告)号：US10114787B2

公开(公告)日：2018-10-30

申请号：US14609488

申请日：2015-01-30

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Yossi Amon ,  Nir Gerber ,  Assaf Shacham

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40 ,  H04L29/12

Abstract: Device identification generation in electronic devices to allow external control, such as selection or reprogramming, of device identification for bus communications identification, is disclosed. In this manner, device identifications of electronic devices coupled to a common communications bus in a system can be selected or reprogrammed to ensure they are unique to avoid bus communications collisions. In certain aspects, to select or reprogram a device identification in an electronic device, an external source can be electrically coupled to the electronic device. The external source closes a circuit with a device identification generation circuit in the electronic device. The closed circuit provides a desired electrical characteristic detectable by the device identification generation circuit. The device identification generation circuit is configured to generate a device identification as a function of the detected electrical characteristics of the closed circuit from the external source.

公开(公告)号：US20150378955A1

公开(公告)日：2015-12-31

申请号：US14316026

申请日：2014-06-26

Applicant: QUALCOMM Incorporated

Inventor： Yossi Amon ,  David Asher Friedman ,  Ben Levin ,  Sharon Graif

IPC: G06F13/42 ,  G06F13/364

CPC classification number: G06F13/4226 ,  G06F13/364 ,  G06F13/4291

Abstract: Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media are disclosed. In one aspect, a method for generating combined bus clock signals comprises detecting a start event by each master device of multiple master devices communicatively coupled to a shared clock line of a shared bus. Each master device samples a plurality of shared clock line values of the shared clock line at a corresponding plurality of transitions of a reference clock signal for the master device. Each master device determines whether the plurality of shared clock line values is identical. If the shared clock line values are identical, each master device drives a shared clock line drive value inverse to the plurality of shared clock line values to the shared clock line at a next transition of the reference clock signal for the master device.

Abstract translation: 公开了在共享总线系统中使用异步主设备参考时钟生成组合总线时钟信号，以及相关方法，设备和计算机可读介质。 一方面，一种用于产生组合总线时钟信号的方法包括：通过通信耦合到共享总线的共享时钟线的多个主设备的每个主设备检测起始事件。 每个主设备在主设备的参考时钟信号的相应多个转换处对共享时钟线的多个共享时钟线值进行采样。 每个主设备确定多个共享时钟线值是否相同。 如果共享时钟线路值相同，则在主设备的参考时钟信号的下一个转换处，每个主设备将共享时钟线驱动值与多个共享时钟线路值相反地驱动到共享时钟线路。