公开(公告)号：US20150134862A1

公开(公告)日：2015-05-14

申请号：US14535992

申请日：2014-11-07

Applicant: QUALCOMM Incorporated

Inventor： Gilad Sthoeger ,  Michael Zilberstein ,  Alexander Khazin ,  Ben Levin

IPC: G06F13/42 ,  G06F1/12

CPC classification number: G06F13/4282 ,  G06F1/12 ,  G06F13/423 ,  G06F13/4291 ,  Y02D10/14 ,  Y02D10/151

Abstract: A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line.

Abstract translation: 串行低功率芯片间媒体总线通信链路部署在具有多个集成电路设备的设备中。 可以确定耦合到通信链路的设备的通信能力，并且可以基于能力将配置或成帧消息发送到第一设备。 消息可以在具有用于控制至少主数据线上的传输定时的时钟的通信链路的主数据线上发送。 通信能力可以包括识别由设备支持或耦合到设备的多个数据线的信息。 第一设备可以被配置为通过辅助数据线与第二设备进行通信，次级数据线可以被保留用于这种直接通信。 次数据线上的通信可以使用时钟信号同步，并且可以由与用于主数据线的协议不同的协议来控制。

公开(公告)号：US20180225251A1

公开(公告)日：2018-08-09

申请号：US15942277

申请日：2018-03-30

Applicant: QUALCOMM Incorporated

Inventor： Gilad Sthoeger ,  Michael Zilbershtein ,  Alexander Khazin ,  Ben Levin

IPC: G06F13/42 ,  G06F1/12

CPC classification number: G06F13/4282 ,  G06F1/12 ,  G06F13/423 ,  G06F13/4291 ,  Y02D10/14 ,  Y02D10/151

Abstract: A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line.

公开(公告)号：US09524264B2

公开(公告)日：2016-12-20

申请号：US14316026

申请日：2014-06-26

Applicant: QUALCOMM Incorporated

Inventor： Yossi Amon ,  David Asher Friedman ,  Ben Levin ,  Sharon Graif

IPC: G06F13/36 ,  G06F13/42 ,  G06F13/364

CPC classification number: G06F13/4226 ,  G06F13/364 ,  G06F13/4291

Abstract: Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media are disclosed. In one aspect, a method for generating combined bus clock signals comprises detecting a start event by each master device of multiple master devices communicatively coupled to a shared clock line of a shared bus. Each master device samples a plurality of shared clock line values of the shared clock line at a corresponding plurality of transitions of a reference clock signal for the master device. Each master device determines whether the plurality of shared clock line values is identical. If the shared clock line values are identical, each master device drives a shared clock line drive value inverse to the plurality of shared clock line values to the shared clock line at a next transition of the reference clock signal for the master device.

Abstract translation: 公开了在共享总线系统中使用异步主设备参考时钟生成组合总线时钟信号，以及相关方法，设备和计算机可读介质。 一方面，一种用于产生组合总线时钟信号的方法包括：通过通信耦合到共享总线的共享时钟线的多个主设备的每个主设备检测起始事件。 每个主设备在主设备的参考时钟信号的相应多个转换处对共享时钟线的多个共享时钟线值进行采样。 每个主设备确定多个共享时钟线值是否相同。 如果共享时钟线路值相同，则在主设备的参考时钟信号的下一个转换处，每个主设备将共享时钟线驱动值与多个共享时钟线路值相反地驱动到共享时钟线路。

公开(公告)号：US10509761B2

公开(公告)日：2019-12-17

申请号：US15942277

申请日：2018-03-30

Applicant: QUALCOMM Incorporated

Inventor： Gilad Sthoeger ,  Michael Zilbershtein ,  Alexander Khazin ,  Ben Levin

IPC: G06F13/42 ,  G06F1/12

Abstract: A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line.

公开(公告)号：US09904652B2

公开(公告)日：2018-02-27

申请号：US14535992

申请日：2014-11-07

Applicant: QUALCOMM Incorporated

Inventor： Gilad Sthoeger ,  Michael Zilberstein ,  Alexander Khazin ,  Ben Levin

IPC: G06F13/42 ,  G06F1/12

CPC classification number: G06F13/4282 ,  G06F1/12 ,  G06F13/423 ,  G06F13/4291 ,  Y02D10/14 ,  Y02D10/151

Abstract: A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line.

公开(公告)号：US20180143938A1

公开(公告)日：2018-05-24

申请号：US15875937

申请日：2018-01-19

Applicant: QUALCOMM Incorporated

Inventor： Gilad Sthoeger ,  Michael Zilbershtein ,  Alexander Khazin ,  Ben Levin

IPC: G06F13/42 ,  G06F1/12

CPC classification number: G06F13/4282 ,  G06F1/12 ,  G06F13/423 ,  G06F13/4291 ,  Y02D10/14 ,  Y02D10/151

Abstract: A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line.

公开(公告)号：US20150378955A1

公开(公告)日：2015-12-31

申请号：US14316026

申请日：2014-06-26

Applicant: QUALCOMM Incorporated

Inventor： Yossi Amon ,  David Asher Friedman ,  Ben Levin ,  Sharon Graif

IPC: G06F13/42 ,  G06F13/364

CPC classification number: G06F13/4226 ,  G06F13/364 ,  G06F13/4291

Abstract: Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media are disclosed. In one aspect, a method for generating combined bus clock signals comprises detecting a start event by each master device of multiple master devices communicatively coupled to a shared clock line of a shared bus. Each master device samples a plurality of shared clock line values of the shared clock line at a corresponding plurality of transitions of a reference clock signal for the master device. Each master device determines whether the plurality of shared clock line values is identical. If the shared clock line values are identical, each master device drives a shared clock line drive value inverse to the plurality of shared clock line values to the shared clock line at a next transition of the reference clock signal for the master device.

Abstract translation: 公开了在共享总线系统中使用异步主设备参考时钟生成组合总线时钟信号，以及相关方法，设备和计算机可读介质。 一方面，一种用于产生组合总线时钟信号的方法包括：通过通信耦合到共享总线的共享时钟线的多个主设备的每个主设备检测起始事件。 每个主设备在主设备的参考时钟信号的相应多个转换处对共享时钟线的多个共享时钟线值进行采样。 每个主设备确定多个共享时钟线值是否相同。 如果共享时钟线路值相同，则在主设备的参考时钟信号的下一个转换处，每个主设备将共享时钟线驱动值与多个共享时钟线路值相反地驱动到共享时钟线路。