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1.发明授权公开(公告)号：US11206157B1
公开(公告)日：2021-12-21
申请号：US17067776
申请日：2020-10-12
Applicant: PHISON ELECTRONICS CORP.
Inventor： Zhen-Hong Hung , Sheng-Wen Chen , Shih-Yang Sun
Abstract: A calibration method of an equalizer circuit for a memory storage device is disclosed. The calibration method includes: receiving a first signal; adjusting, by the equalizer circuit, the first signal according to a control parameter to output a second signal; generating a first sampling signal according to a first reference signal and the second signal, wherein the first sampling signal reflects data transmitted by the first signal; and generating a second sampling signal according to a second reference signal and the second signal and adjusting the control parameter according to the second sampling signal to calibrate the equalizer circuit, wherein a voltage value of the first reference signal is different from a voltage value of the second reference signal.
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公开(公告)号：US20190116069A1
公开(公告)日：2019-04-18
申请号：US15836903
申请日：2017-12-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Sheng-Wen Chen , Shin-Yang Sun , Wei-Yung Chen , Jen-Chu Wu , Chih-Ming Chen
IPC: H04L25/03 , G06F3/06 , H04L7/00 , H04L25/497
Abstract: An equalizer tuning method for a memory storage device is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal; modulating the first signal by a first modulation circuit according to a first type parameter and modulating the first signal by a second modulation circuit according to a second type parameter; detecting a signal eye-width value and a signal eye-height value of the modulated first signal; and adjusting the first type parameter according to the detected signal eye-width value and adjusting the second type parameter according to the detected signal eye-height value.
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3.发明授权Data sampling circuit module, data sampling method and memory storage device 有权数据采样电路模块，数据采样方法和存储器存储装置公开(公告)号：US09349473B1
公开(公告)日：2016-05-24
申请号：US14619074
申请日：2015-02-11
Applicant: PHISON ELECTRONICS CORP.
Inventor： Sheng-Wen Chen , Wei-Yung Chen
CPC classification number: G11C16/28 , G11C7/062 , G11C27/02 , G11C27/024
Abstract: A data sampling circuit module, a data sampling method and a memory storage device are provided. The method includes: receiving a differential signal and generating a sensing voltage pair according to the differential signal, where the sensing voltage pair includes a first sensing voltage and a second sensing voltage, a voltage value of the first sensing voltage is related to a first differential signal of the differential signal, and a voltage value of the second sensing voltage is related to a second differential signal of the differential signal; and receiving the sensing voltage pair and outputting a sampling data stream according to a clock of the differential signal and a voltage relative relationship of the sensing voltage pair.
Abstract translation: 提供数据采样电路模块，数据采样方法和存储器存储装置。 该方法包括：接收差分信号并根据差分信号产生感测电压对，其中感测电压对包括第一感测电压和第二感测电压，第一感测电压的电压值与第一差分 差分信号的信号和第二感测电压的电压值与差分信号的第二差分信号相关; 并接收感测电压对，并根据差分信号的时钟和感测电压对的电压相对关系输出采样数据流。
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公开(公告)号：US20230035428A1
公开(公告)日：2023-02-02
申请号：US17458548
申请日：2021-08-27
Applicant: PHISON ELECTRONICS CORP.
Inventor： Po-Jung Chou , Sheng-Wen Chen , Chung-Kuang Chen
Abstract: A signal re-driving device, a data storage system and a mode control method are provided. The method includes the following steps. A first signal is received via a receiving circuit of the signal re-driving device. An analog signal feature is detected the receiving circuit. A first mode is entered according to the analog signal feature. The first signal is modulated and a second signal is outputted in the first mode. The second signal is sent via a sending circuit of the signal re-driving device. A digital signal feature is detected via the receiving circuit. And, the first mode is switched to a second mode according to the digital signal feature.
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公开(公告)号：US11062781B1
公开(公告)日：2021-07-13
申请号：US16916137
申请日：2020-06-30
Applicant: PHISON ELECTRONICS CORP.
Inventor： Zhen-Hong Hung , Shih-Yang Sun , Sheng-Wen Chen
IPC: G11C16/32
Abstract: An equalizer circuit, a memory storage device and a signal adjustment method are disclosed. The equalizer circuit is configured to receive an input signal, a reference voltage signal and a sensing clock signal and generate an error signal. The equalizer circuit is further configured to generate a first adjustment signal and a second adjustment signal according to the error signal. The equalizer circuit is further configured to update a control code from a first control code to a second control code according to at least one of the first adjustment signal and the second adjustment signal and generate an adjustment control signal according to the control code. The equalizer circuit is further configured to generate a feedback control signal according to the adjustment control signal to restore the control code from the second control code to the first control code.
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Patent Agency Ranking
公开(公告)号：US10965438B1
公开(公告)日：2021-03-30
申请号：US16779666
申请日：2020-02-03
Applicant: PHISON ELECTRONICS CORP.
Inventor： Shih-Yang Sun , Sheng-Wen Chen , Yen-Po Lin , Bo-Jing Lin , Po-Min Cheng
Abstract: A signal receiving circuit, a memory storage device and a signal receiving method are provided. The signal receiving circuit includes an equalizer module, a clock and data recovery (CDR) circuit and a controller. The equalizer module is configured to receive a first signal and compensate the first signal to generate a second signal. The CDR circuit is configured to perform a phase locking on the second signal. The controller is configured to open or close a signal pattern filter of the CDR circuit according to the second signal, wherein the signal pattern filter is configured to filter a signal having a specific pattern in the second signal.
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公开(公告)号：US10326622B2
公开(公告)日：2019-06-18
申请号：US15836903
申请日：2017-12-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Sheng-Wen Chen , Shin-Yang Sun , Wei-Yung Chen , Jen-Chu Wu , Chih-Ming Chen
IPC: H04L25/03 , H04L25/497 , H04L7/00 , G06F3/06
Abstract: An equalizer tuning method for a memory storage device is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal; modulating the first signal by a first modulation circuit according to a first type parameter and modulating the first signal by a second modulation circuit according to a second type parameter; detecting a signal eye-width value and a signal eye-height value of the modulated first signal; and adjusting the first type parameter according to the detected signal eye-width value and adjusting the second type parameter according to the detected signal eye-height value.
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公开(公告)号：US09467314B1
公开(公告)日：2016-10-11
申请号：US14855389
申请日：2015-09-16
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei-Ting Wei , Sheng-Wen Chen , Wei-Yung Chen , Chih-Ming Chen
IPC: H04L25/03
CPC classification number: H04L25/03057 , H04L7/0058
Abstract: A signal modulation method, an adaptive equalizer and a memory storage device are provided. The method includes: receiving a first signal; performing a first modulation on the first signal based on a first power mode to generate a second signal having a first eye-width; performing a second modulation based on a second power mode to generate the second signal having a second eye-width; determining whether the first eye-width and the second eye-width meet a first condition; if yes, performing a third modulation based on the first power mode to generate the second signal having a third eye-width; otherwise, performing the third modulation based on the second power mode to generate the second signal having the third eye-width. Therein, a power consumption of performing the second modulation is less than that of performing the first modulation. Therefore, an efficiency of the adaptive equalizer may be improved.
Abstract translation: 提供信号调制方法，自适应均衡器和存储器存储装置。 该方法包括：接收第一信号; 基于第一功率模式对所述第一信号执行第一调制以产生具有第一眼睛宽度的第二信号; 基于第二功率模式执行第二调制以产生具有第二眼睛宽度的第二信号; 确定第一眼睛宽度和第二眼睛宽度是否满足第一条件; 如果是，则基于第一功率模式执行第三调制以产生具有第三眼睛宽度的第二信号; 否则，基于第二功率模式执行第三调制以产生具有第三眼睛宽度的第二信号。 其中，执行第二调制的功耗小于执行第一调制的功耗。 因此，可以提高自适应均衡器的效率。
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公开(公告)号：US11886263B2
公开(公告)日：2024-01-30
申请号：US17458548
申请日：2021-08-27
Applicant: PHISON ELECTRONICS CORP.
Inventor： Po-Jung Chou , Sheng-Wen Chen , Chung-Kuang Chen
CPC classification number: G06F1/26 , G06F13/4022
Abstract: A signal re-driving device, a data storage system and a mode control method are provided. The method includes the following steps. A first signal is received via a receiving circuit of the signal re-driving device. An analog signal feature is detected the receiving circuit. A first mode is entered according to the analog signal feature. The first signal is modulated and a second signal is outputted in the first mode. The second signal is sent via a sending circuit of the signal re-driving device. A digital signal feature is detected via the receiving circuit. And, the first mode is switched to a second mode according to the digital signal feature.
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公开(公告)号：US11575496B1
公开(公告)日：2023-02-07
申请号：US17547241
申请日：2021-12-10
Applicant: PHISON ELECTRONICS CORP.
Inventor： Jen-Chu Wu , Ching-Jui Hsiao , Chun-Wei Chang , Sheng-Wen Chen , Ching-Chung Cheng
Abstract: A retiming circuit module, a signal transmission system and a signal transmission method are disclosed. The retiming circuit module includes a path control circuit and a multipath signal transmission circuit. The multipath signal transmission circuit includes a plurality of parallel signal transmission paths. The path control circuit is configured to control the multipath signal transmission circuit to perform signal transmission between an upstream device and a downstream device based on a first parallel signal transmission path in the parallel signal transmission paths during a period of a handshake operation performed between the upstream device and the downstream device. The path control circuit is further configured to control the multipath signal transmission circuit to perform the signal transmission based on a second parallel signal transmission path in the parallel signal transmission paths after the handshake operation is finished.
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