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公开(公告)号：US12249999B2
公开(公告)日：2025-03-11
申请号：US18171211
申请日：2023-02-17
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Rui Wang , Hiroaki Ebihara
Abstract: A pixel cell readout circuit comprises a ramp generator having a ramp generator output. A first gain network is coupled to the ramp generator output and configured to provide a first variable comparator gain. A second gain network is coupled to the ramp generator output and configured to provide a second variable comparator gain. A first comparator has a first input coupled to the first gain network. The first comparator further has a second input selectively coupled to a first bitline and selectively coupled to a second bitline. A second comparator has a first input coupled to the second gain network. The second comparator further has a second input selectively coupled to the first bitline and selectively coupled to the second bitline.
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公开(公告)号：US20240397236A1
公开(公告)日：2024-11-28
申请号：US18322408
申请日：2023-05-23
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Hiroaki Ebihara , Jiayu Guo , Liang Zuo , Lihang Fan
IPC: H04N25/78 , H04N25/616
Abstract: A readout circuit includes a comparator having a first input coupled to receive a ramp signal from a ramp generator and a second input coupled to receive an analog image data signal from one of a plurality of bitlines. The comparator is configured to generate a comparator output in response to a comparison of the ramp signal and the analog image data signal. A sampling circuit has a first input coupled to receive a sampling control signal and a second input coupled to receive the comparator output. The sampling circuit is configured to generate a sampling output. A counter has a first input coupled to receive a counter control signal and a second input coupled to receive one of the comparator output and a signal from the sampling circuit. The readout circuit is configured to perform correlated multiple sampling (CMS) calculations or non-CMS calculations in response to the sampling output.
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公开(公告)号：US12114092B2
公开(公告)日：2024-10-08
申请号：US18171227
申请日：2023-02-17
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Rui Wang , Hiroaki Ebihara
Abstract: A pixel cell readout circuit comprises a comparator with a current mirror having first and second current paths, a first input transistor coupled to the first current path, a low conversion gain (LCG) second input transistor selectively coupled to the second current path, and a high conversion gain (HCG) second input transistor selectively coupled to the second current path. The pixel cell readout circuit further comprises a gain network coupled between a gate node of the first input transistor and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator, an LCG auto-zero switch coupled between a drain node and a gate node of the LCG second input transistor, and an HCG auto-zero switch coupled between a drain node and a gate node of the HCG second input transistor.
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4.发明公开公开(公告)号：US20240314460A1
公开(公告)日：2024-09-19
申请号：US18393135
申请日：2023-12-21
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Amit Mittra , Kevin Johnson , Hiroaki Ebihara , Kenny Geng
Abstract: A pixel includes a photosensor configured to photogenerate charge in response to incident light. A floating diffusion is configured to receive the charge photogenerated by the photosensor. A transfer transistor is coupled between the floating diffusion and the photosensor. A dual floating diffusion (DFD) transistor is coupled to the floating diffusion. A binning node is coupled to the DFD transistor. A floating diffusion interconnect grid is coupled to the binning node of the pixel and a binning node of a second pixel. The pixel and the second pixel are included in a pixel array. The DFD transistor is configured to couple the binning node to the floating diffusion when activated during a readout operation of the pixel array to provide a binned readout, and the DFD transistor is configured not to couple the binning node to the floating diffusion when deactivated to provide a full resolution readout.
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公开(公告)号：US20240283460A1
公开(公告)日：2024-08-22
申请号：US18171211
申请日：2023-02-17
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Rui Wang , Hiroaki Ebihara
Abstract: A pixel cell readout circuit comprises a ramp generator having a ramp generator output. A first gain network is coupled to the ramp generator output and configured to provide a first variable comparator gain. A second gain network is coupled to the ramp generator output and configured to provide a second variable comparator gain. A first comparator has a first input coupled to the first gain network. The first comparator further has a second input selectively coupled to a first bitline and selectively coupled to a second bitline. A second comparator has a first input coupled to the second gain network. The second comparator further has a second input selectively coupled to the first bitline and selectively coupled to the second bitline.
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Patent Agency Ranking
公开(公告)号：US11722801B1
公开(公告)日：2023-08-08
申请号：US17659042
申请日：2022-04-13
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Hiroaki Ebihara , Zhenfu Tian , Tao Sun , Liang Zuo , Yu-Shen Yang , Satoshi Sakurai , Rui Wang
IPC: H04N25/75 , H04N25/772
CPC classification number: H04N25/75 , H04N25/772
Abstract: A ramp buffer circuit includes an input device having an input coupled to receive a ramp signal. A bias current source is coupled to an output of the input device. The input device and the bias current source are coupled between a power line and ground. An assist current source is coupled between the output of the input device and ground. The assist current source is configured to conduct an assist current from the output of the input device to ground only during a ramp event generated in the ramp signal.
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公开(公告)号：US11290674B1
公开(公告)日：2022-03-29
申请号：US17127571
申请日：2020-12-18
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Hiroaki Ebihara
IPC: H04N5/378 , H01L27/146 , H04N5/374 , H04N5/3745
Abstract: A pixel cell readout circuit includes an amplifier and a capacitor switch circuit that includes a first routing path coupled to an input of the amplifier. A second routing path includes switches coupled in series along the second routing path. A first end of the second routing path is coupled to a bitline. A second end of the second routing path is coupled to an output of the amplifier. Only one of the switches is turned off and a remainder of the switches are turned on. Capacitors are coupled in parallel between the first routing path and the second routing path. A first end of each of the capacitors is coupled to the first routing path. A second end of each of the capacitors is coupled to the second routing path. The switches are interleaved among the second ends of the capacitors along the second routing path.
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公开(公告)号：US11240456B2
公开(公告)日：2022-02-01
申请号：US16441674
申请日：2019-06-14
Applicant: OmniVision Technologies, Inc.
Inventor： Hiroaki Ebihara , Zheng Yang
IPC: H04N5/378 , H04N5/365 , H04N5/3745 , H01L27/146
Abstract: An amplifier circuit for use in an image sensor includes a common source amplifier coupled to receive an input signal representative of an image charge from a pixel cell of the image sensor. An auto-zero switch is coupled between an input of the common source amplifier and an output of the common source amplifier. A feedback capacitor is coupled to the input of the common source amplifier. An offset switch is coupled to the feedback capacitor and is further coupled to a reset voltage and an output of the amplifier circuit. The auto-zero switch and the offset switch are configured to couple the feedback capacitor to the reset voltage during a reset of the amplifier circuit. The offset switch is configured to couple the feedback capacitor to the output of the amplifier circuit after the reset of the amplifier circuit.
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公开(公告)号：US11206039B1
公开(公告)日：2021-12-21
申请号：US17127499
申请日：2020-12-18
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Hiroaki Ebihara
IPC: H03M1/56 , H03K5/08 , H04N5/3745 , H03M1/46 , H03K5/24
Abstract: A comparator includes a second stage coupled between a first stage and a third stage. The second stage includes a first transistor coupled to be switched in response to a first output signal coupled to be received from the first stage. The first transistor is coupled generate a second output signal coupled to be received by the third stage. A second transistor is coupled to the first transistor. The first and second transistors are coupled between a first supply voltage and a reference voltage. A second stage current of the second stage is conducted through the first transistor and the second transistor. The second transistor is coupled to be switched in response to a third output signal coupled to be received from the third stage in response to the second output signal.
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公开(公告)号：US20210392286A1
公开(公告)日：2021-12-16
申请号：US16900576
申请日：2020-06-12
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Hiroaki Ebihara , Rui Wang , John Brummer , Shan Chen
Abstract: A pixel cell readout circuit includes a bitline input stage coupled to a bitline to receive an image signal from a pixel cell. A capacitor ratio circuit is coupled to the bitline input stage. A gain of the bitline input stage is responsive to a capacitor ratio provided by the capacitor ratio circuit to the bitline input stage. A switch control circuit is coupled to receive a gain signal. The switch control circuit is coupled to generate a randomized pattern selection signal coupled to be received by the capacitor ratio circuit to select the capacitor ratio provided by the capacitor ratio circuit in response to the gain signal.
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