公开(公告)号：US09041129B2

公开(公告)日：2015-05-26

申请号：US14087355

申请日：2013-11-22

Applicant: National Applied Research Laboratories

Inventor： Chia-Hua Ho ,  Ming-Daou Lee ,  Wen-Cheng Chiu ,  Cho-Lun Hsu

IPC: H01L29/82 ,  H01L27/24 ,  H01L27/22 ,  H01L27/105 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/1052 ,  H01L27/222 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1675

Abstract: A semiconductor memory storage array device comprises a first electrode layer, an oxide layer, a second electrode layer, a memory material layer and a first insulator layer. The oxide layer is disposed on the first electrode layer. The second electrode layer is disposed on the oxide layer. The memory material layer is disposed on the second electrode layer. The first insulator layer is disposed adjacent to two sidewalls of the first electrode layer, the oxide layer, the second electrode layer and the memory material layer, so to define a gap either between the first electrode layer and the oxide layer or between the second electrode layer and the oxide layer.

Abstract translation: 半导体存储器存储阵列器件包括第一电极层，氧化物层，第二电极层，存储材料层和第一绝缘体层。 氧化物层设置在第一电极层上。 第二电极层设置在氧化物层上。 存储材料层设置在第二电极层上。 第一绝缘体层邻近第一电极层，氧化物层，第二电极层和存储材料层的两个侧壁设置，以便在第一电极层和氧化物层之间或第二电极之间限定间隙 层和氧化物层。

公开(公告)号：US08987071B2

公开(公告)日：2015-03-24

申请号：US14107742

申请日：2013-12-16

Applicant: National Applied Research Laboratories

Inventor： Min-Cheng Chen ,  Chang-Hsien Lin ,  Chia-Yi Lin ,  Tung-Yen Lai ,  Chia-Hua Ho

IPC: H01L27/12 ,  H01L29/06 ,  B82Y10/00 ,  H01L27/06 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/127 ,  B82Y10/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0676

Abstract: A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed.

Abstract translation: 薄膜晶体管包括半导体板，电介质层，半导体膜层，导电层，源极和漏极。 半导体面板包括基底，介质内介质层，至少一个金属线层和至少一个通孔层。 电介质层堆叠在半导体面板上。 半导体膜层层叠在电介质层上。 导电层形成在半导体膜层上。 源极形成在与通孔相邻并连接到通孔的通孔的通孔上。 漏极形成在邻近并连接到栅极通孔的通孔的另一个通孔上。 还公开了一种具有金属栅极和纳米线的薄膜晶体管的制造方法。