公开(公告)号：US20170012611A1

公开(公告)日：2017-01-12

申请号：US14792276

申请日：2015-07-06

Applicant: NXP B.V.

Inventor： Juan Echeverri Escobar ,  Jose de Jesus Pineda de Gyvez ,  Sebastien Antonius Josephus Fabrie

IPC: H03K3/037

CPC classification number: H03K3/0372 ,  H03K3/012 ,  H03K3/037 ,  H03K19/0016

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.

Abstract translation: 公开了一种装置和方法的实施例。 在一个实施例中，公开了一种触发器电路。 触发器电路包括主锁存器，连接到主锁存器的从锁存器以及连接在主锁存器和从锁存器之间并被配置为执行状态保持和双重采样的双功能电路。

公开(公告)号：US09488691B2

公开(公告)日：2016-11-08

申请号：US14718294

申请日：2015-05-21

Applicant: NXP B.V.

Inventor： Juan Echeverri Escobar ,  Surendra Guntur ,  Manvi Agarwal ,  Rinze Ida Mechtildis Peter Meijer

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3193 ,  H03K3/037

CPC classification number: G01R31/31725 ,  G01R31/31727 ,  G01R31/31937 ,  H03K3/0375

Abstract: An integrated circuit comprises: a first processing stage comprising processing logic for performing a processing operation on an input signal to generate an output signal, wherein the input signal corresponds to an output signal of a previous processing stage; a first sampling element adapted to sample a first value of said output signal synchronously with a clock signal; a second sampling element adapted to sample a second value of said output signal synchronously with a first delayed clock signal; and a first delayed clock signal generator, adapted to selectively generate said first delayed clock signal in response to a control signal generated in said previous processing stage.

Abstract translation: 集成电路包括：第一处理级，包括用于对输入信号执行处理操作以产生输出信号的处理逻辑，其中所述输入信号对应于先前处理级的输出信号; 第一采样元件，适于与时钟信号同步地采样所述输出信号的第一值; 第二采样元件，适于与第一延迟时钟信号同步地采样所述输出信号的第二值; 以及第一延迟时钟信号发生器，其适于响应于在所述先前处理级中产生的控制信号选择性地产生所述第一延迟时钟信号。

公开(公告)号：US09465614B2

公开(公告)日：2016-10-11

申请号：US14195657

申请日：2014-03-03

Applicant: NXP B.V.

Inventor： Hamed Fatemi ,  Jose Pineda de Gyvez ,  Juan Echeverri Escobar

IPC: G06F9/30 ,  G06F1/32 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3885 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24

Abstract: An integrated circuit comprising a set of data processing units including a first data processing unit and at least one second data processing unit operable at variable frequencies is disclosed. The integrated circuit further includes an instruction scheduler adapted to evaluate data dependencies between individual instructions in a received plurality of instructions and assign the instructions to the first data processing unit and the at least one second data processing unit for parallel execution in accordance with said data dependencies. The integrated circuit is operable in a first power mode and a second power mode. The second power mode is a reduced power mode compared to the first power mode and is adapted to adjust the operating frequency of the first data processing unit and the at least one second data processing unit in the second power mode as a function of the evaluated data dependencies.

Abstract translation: 一种集成电路，包括一组数据处理单元，包括第一数据处理单元和至少一个以可变频率工作的第二数据处理单元。 集成电路还包括指令调度器，其适于评估接收的多个指令中的各个指令之间的数据依赖性，并且将指令分配给第一数据处理单元和至少一个第二数据处理单元，用于根据所述数据依赖性进行并行执行 。 集成电路可在第一功率模式和第二功率模式下操作。 第二功率模式是与第一功率模式相比的降低功率模式，并且适于根据评估数据调整第二数据处理单元和第二功率模式中的至少一个第二数据处理单元的工作频率 依赖关系。

公开(公告)号：US20150372666A1

公开(公告)日：2015-12-24

申请号：US14718294

申请日：2015-05-21

Applicant: NXP B.V.

Inventor： Juan Echeverri Escobar ,  Surendra Guntur ,  Manvi Agarwal ,  Rinze Ida Mechtildis Peter Meijer

IPC: H03K5/13

CPC classification number: G01R31/31725 ,  G01R31/31727 ,  G01R31/31937 ,  H03K3/0375

Abstract: An integrated circuit comprises: a first processing stage comprising processing logic for performing a processing operation on an input signal to generate an output signal wherein the input signal corresponds to an output signal of a previous processing stage; a first sampling element adapted to sample a first value of said output signal synchronously with a clock signal; a second sampling element adapted to sample a second value of said output signal synchronously with a first delayed clock signal; and a first delayed clock signal generator, adapted to selectively generate said first delayed clock signal in response to a control signal generated in said previous processing stage.

Abstract translation: 集成电路包括：第一处理级，包括用于对输入信号执行处理操作的处理逻辑，以产生输出信号，其中输入信号对应于先前处理级的输出信号; 第一采样元件，适于与时钟信号同步地采样所述输出信号的第一值; 第二采样元件，适于与第一延迟时钟信号同步地采样所述输出信号的第二值; 以及第一延迟时钟信号发生器，其适于响应于在所述先前处理级中产生的控制信号选择性地产生所述第一延迟时钟信号。

公开(公告)号：US10534396B2

公开(公告)日：2020-01-14

申请号：US15911901

申请日：2018-03-05

Applicant: NXP B.V.

Inventor： Sebastien Fabrie ,  Juan Echeverri Escobar ,  Jose Pineda De Gyvez

IPC: G06F1/12 ,  G06F11/16 ,  H04L7/00 ,  G01R31/317 ,  G06F11/00

Abstract: There is disclosed a synchronous digital circuit having a system clock and for processing a data signal, wherein the digital circuit comprises a data path, a hard macro having a macro input, a logic circuit in the data path upstream of the macro input and having a first part and a second part, the second part being immediately upstream of the macro input, a set-up timing error detector having an input, wherein the input is on the data path between the first part and the second part, and a timing correction unit, wherein the data transit time across the second part is equal to or less than one half of a clock period, and wherein the timing correction unit is configured to correct, in response to the set-up timing error detector detecting a set-up timing error, the detected set-up timing error before the data reaches the macro input.

公开(公告)号：US09634649B2

公开(公告)日：2017-04-25

申请号：US14792276

申请日：2015-07-06

Applicant: NXP B.V.

Inventor： Juan Echeverri Escobar ,  Jose de Jesus Pineda de Gyvez ,  Sebastien Antonius Josephus Fabrie

IPC: H03K3/289 ,  H03K3/356 ,  H03K3/037

CPC classification number: H03K3/0372 ,  H03K3/012 ,  H03K3/037 ,  H03K19/0016

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.

公开(公告)号：US20140258686A1

公开(公告)日：2014-09-11

申请号：US14195657

申请日：2014-03-03

Applicant: NXP B.V.

Inventor： Hamed Fatemi ,  Jose Pineda de Gyvez ,  Juan Echeverri Escobar

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3885 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24

Abstract: An integrated circuit comprising a set of data processing units including a first data processing unit and at least one second data processing unit operable at variable frequencies is disclosed. The integrated circuit further includes an instruction scheduler adapted to evaluate data dependencies between individual instructions in a received plurality of instructions and assign the instructions to the first data processing unit and the at least one second data processing unit for parallel execution in accordance with said data dependencies. The integrated circuit is operable in a first power mode and a second power mode. The second power mode is a reduced power mode compared to the first power mode and is adapted to adjust the operating frequency of the first data processing unit and the at least one second data processing unit in the second power mode as a function of the evaluated data dependencies.

Abstract translation: 一种集成电路，包括一组数据处理单元，包括第一数据处理单元和至少一个以可变频率工作的第二数据处理单元。 集成电路还包括指令调度器，其适于评估接收的多个指令中的各个指令之间的数据依赖性，并且将指令分配给第一数据处理单元和至少一个第二数据处理单元，用于根据所述数据依赖性进行并行执行 。 集成电路可在第一功率模式和第二功率模式下操作。 第二功率模式是与第一功率模式相比的降低功率模式，并且适于根据评估数据调整第二数据处理单元和第二功率模式中的至少一个第二数据处理单元的工作频率 依赖关系。