公开(公告)号：US10534396B2

公开(公告)日：2020-01-14

申请号：US15911901

申请日：2018-03-05

Applicant: NXP B.V.

Inventor： Sebastien Fabrie ,  Juan Echeverri Escobar ,  Jose Pineda De Gyvez

IPC: G06F1/12 ,  G06F11/16 ,  H04L7/00 ,  G01R31/317 ,  G06F11/00

Abstract: There is disclosed a synchronous digital circuit having a system clock and for processing a data signal, wherein the digital circuit comprises a data path, a hard macro having a macro input, a logic circuit in the data path upstream of the macro input and having a first part and a second part, the second part being immediately upstream of the macro input, a set-up timing error detector having an input, wherein the input is on the data path between the first part and the second part, and a timing correction unit, wherein the data transit time across the second part is equal to or less than one half of a clock period, and wherein the timing correction unit is configured to correct, in response to the set-up timing error detector detecting a set-up timing error, the detected set-up timing error before the data reaches the macro input.