公开(公告)号：US09762906B2

公开(公告)日：2017-09-12

申请号：US14179540

申请日：2014-02-12

Applicant: MEDIATEK INC.

Inventor： Chia-Yun Cheng ,  Huei-Min Lin ,  Yung-Chang Chang

IPC: H04N19/436 ,  H04N19/82 ,  H04N19/86 ,  H04N19/51

CPC classification number: H04N19/865 ,  H04N19/436 ,  H04N19/51 ,  H04N19/82

Abstract: A method and apparatus for deblocking process using multiple processing units are disclosed. The video image is divided into at least two regions. The in-loop filter is applied to block boundaries associated with said at least two regions using multiple processing units. The in-loop filter is re-applied to one or more second block boundaries adjacent to region edge between two regions after applying the in-loop filter to the first block boundaries adjacent to the region edge. Furthermore, at least a first portion of said applying the in-loop filter to the first block boundaries and a second portion of said applying the in-loop filter to the second block boundaries are performed concurrently. The multiple processing units may correspond to multiple processing cores within one processor chip.

公开(公告)号：US20180139464A1

公开(公告)日：2018-05-17

申请号：US15803388

申请日：2017-11-03

Applicant: MEDIATEK INC.

Inventor： Min-Hao CHIU ,  Ping Chao ,  Chia-Hung Kao ,  Huei-Min Lin ,  Hsiu-Yi Lin ,  Chi-Hung Chen ,  Chia-Yun Cheng ,  Chih-Ming Wang ,  Yung-Chang Chang

IPC: H04N19/44 ,  H04N19/423 ,  H04N19/172

Abstract: Aspects of the disclosure provide a video decoding system. The video decoding system can include a decoder core configured to selectively decode independently decodable tiles in a picture, each tile including largest coding units (LCUs) each associated with a pair of picture-based (X, Y) coordinates or tile-based (X, Y) coordinates, and memory management circuitry configured to translate one or two coordinates of a current LCU to generate one or two translated coordinates, and to determine a target memory space storing reference data for decoding the current LCU based on the one or two translated coordinates.

公开(公告)号：US09635360B2

公开(公告)日：2017-04-25

申请号：US13922481

申请日：2013-06-20

Applicant: MEDIATEK INC.

Inventor： Ping Chao ,  Huei-Min Lin ,  Yung-Chang Chang ,  Chi-Cheng Ju

IPC: H04N19/86 ,  H04N19/176 ,  H04N19/117 ,  H04N19/156 ,  H04N19/82

CPC classification number: H04N19/86 ,  H04N19/117 ,  H04N19/156 ,  H04N19/176 ,  H04N19/82

Abstract: A method and apparatus for applying DF processing and SAO processing to reconstructed video data are disclosed. The DF processing is applied to a current access element of reconstructed video data to generate DF output data and the deblocking status is determined while applying the DF processing. Status-dependent SAO processing is applied to one or more pixels of the DF output data according to the deblocking status. The status-dependent SAO processing comprises SAO processing, partial SAO processing, and no SAO processing. The SAO starting time for SAO processing is between the DF-output starting time and ending time for the current block. The DF starting time of a next block can be earlier than the SAO ending time of the current block by a period oft, where t is smaller than time difference between the DF-output starting time and the DF starting time of the next block.

公开(公告)号：US20140036992A1

公开(公告)日：2014-02-06

申请号：US13922481

申请日：2013-06-20

Applicant: MEDIATEK INC.

Inventor： Ping Chao ,  Huei-Min Lin ,  Yung-Chang Chang ,  Chi-Cheng Ju

IPC: H04N7/26

CPC classification number: H04N19/86 ,  H04N19/117 ,  H04N19/156 ,  H04N19/176 ,  H04N19/82

Abstract: A method and apparatus for applying DF processing and SAO processing to reconstructed video data are disclosed. The DF processing is applied to a current access element of reconstructed video data to generate DF output data and the deblocking status is determined while applying the DF processing. Status-dependent SAO processing is applied to one or more pixels of the DF output data according to the deblocking status. The status-dependent SAO processing comprises SAO processing, partial SAO processing, and no SAO processing. The SAO starting time for SAO processing is between the DF-output starting time and ending time for the current block. The DF starting time of a next block can be earlier than the SAO ending time of the current block by a period oft, where t is smaller than time difference between the DF-output starting time and the DF starting time of the next block.

Abstract translation: 公开了一种用于对重构的视频数据应用DF处理和SAO处理的方法和装置。 DF处理被应用于重构的视频数据的当前访问元件以产生DF输出数据，并且在应用DF处理的同时确定去块状态。 根据去块状态，将状态依赖的SAO处理应用于DF输出数据的一个或多个像素。 状态依赖性SAO处理包括SAO处理，部分SAO处理，无SAO处理。 SAO处理的SAO启动时间在当前块的DF输出开始时间和结束时间之间。 下一个块的DF开始时间可以比当前块的SAO结束时间早一个时间t，其中t小于DF输出开始时间和下一个块的DF开始时间之间的时间差。

公开(公告)号：US09438911B2

公开(公告)日：2016-09-06

申请号：US13944893

申请日：2013-07-18

Applicant: MEDIATEK INC.

Inventor： Huei-Min Lin ,  Ping Chao ,  Chi-Cheng Ju ,  Yung-Chang Chang

IPC: H04N19/00 ,  H04N19/80 ,  H04N19/423

CPC classification number: H04N19/80 ,  H04N19/423

Abstract: A video processing system includes a data buffer and a storage controller. The data buffer is shared between a plurality of in-loop filters, wherein not all of the in-loop filters comply with a same video standard. The storage controller controls data access of the data buffer, wherein for each in-loop filter granted to access the data buffer, the data buffer stores a partial data of a picture processed by the in-loop filter. Another video processing system includes a storage device and a storage controller. The storage controller adaptively determines a size of a storage space according to a tile partition setting of a picture to be processed by an in-loop filter, and controls the storage device to allocate the storage space to serve as a data buffer for storing data of the in-loop filter.

Abstract translation: 视频处理系统包括数据缓冲器和存储控制器。 数据缓冲器在多个环路滤波器之间共享，其中并非所有的环路滤波器都符合相同的视频标准。 存储控制器控制数据缓冲器的数据访问，其中对于被授权访问数据缓冲器的每个环路滤波器，数据缓冲器存储由环路滤波器处理的图像的部分数据。 另一视频处理系统包括存储设备和存储控制器。 存储控制器根据由环路过滤器处理的图像的瓦片分区设置自适应地确定存储空间的大小，并且控制存储设备分配存储空间以用作用于存储数据的数据的数据缓冲器 内置滤波器。

公开(公告)号：US20160029022A1

公开(公告)日：2016-01-28

申请号：US14806664

申请日：2015-07-23

Applicant: MEDIATEK INC.

Inventor： Chia-Yun Cheng ,  Chih-Ming Wang ,  Yung-Chang Chang ,  Chun-Chia Chen ,  Meng-Jye Hu ,  Huei-Min Lin

IPC: H04N19/119 ,  H04N19/91

CPC classification number: H04N19/119 ,  H04N19/157 ,  H04N19/176 ,  H04N19/91 ,  H04N19/96

Abstract: A video processing apparatus includes a first processing circuit, a second processing circuit, and a control circuit. The first processing circuit performs a first processing operation. The second processing circuit performs a second processing operation different from the first processing operation. The control circuit generates at least one output coding unit to the second processing circuit according to an input coding unit generated from the first processing circuit, wherein the control circuit checks a size of the input coding unit to selectively split the input coding unit into a plurality of output coding units.

Abstract translation: 视频处理装置包括第一处理电路，第二处理电路和控制电路。 第一处理电路执行第一处理操作。 第二处理电路执行与第一处理操作不同的第二处理操作。 所述控制电路根据从所述第一处理电路产生的输入编码单元，向所述第二处理电路生成至少一个输出编码单元，其中，所述控制电路检查所述输入编码单元的大小，以选择性地将所述输入编码单元分割成多个 的输出编码单元。

公开(公告)号：US20140037017A1

公开(公告)日：2014-02-06

申请号：US13944893

申请日：2013-07-18

Applicant: MEDIATEK INC.

Inventor： Huei-Min Lin ,  Ping Chao ,  Chi-Cheng Ju ,  Yung-Chang Chang

IPC: H04N7/26

CPC classification number: H04N19/80 ,  H04N19/423

Abstract: A video processing system includes a data buffer and a storage controller. The data buffer is shared between a plurality of in-loop filters, wherein not all of the in-loop filters comply with a same video standard. The storage controller controls data access of the data buffer, wherein for each in-loop filter granted to access the data buffer, the data buffer stores a partial data of a picture processed by the in-loop filter. Another video processing system includes a storage device and a storage controller. The storage controller adaptively determines a size of a storage space according to a tile partition setting of a picture to be processed by an in-loop filter, and controls the storage device to allocate the storage space to serve as a data buffer for storing data of the in-loop filter.

Abstract translation: 视频处理系统包括数据缓冲器和存储控制器。 数据缓冲器在多个环路滤波器之间共享，其中并非所有的环路滤波器都符合相同的视频标准。 存储控制器控制数据缓冲器的数据访问，其中对于被授权访问数据缓冲器的每个环路滤波器，数据缓冲器存储由环路滤波器处理的图像的部分数据。 另一视频处理系统包括存储设备和存储控制器。 存储控制器根据由环路过滤器处理的图像的瓦片分区设置自适应地确定存储空间的大小，并且控制存储设备分配存储空间以用作用于存储数据的数据的数据缓冲器 内置滤波器。

公开(公告)号：US10592321B2

公开(公告)日：2020-03-17

申请号：US15974701

申请日：2018-05-09

Applicant: MEDIATEK INC.

Inventor： Huei-Min Lin ,  Yi-Chang Chen ,  Chih-Ming Wang ,  Yung-Chang Chang

IPC: G06F11/00 ,  G05B9/02 ,  G06F1/08 ,  G06F3/06

Abstract: A data processing system includes a buffer, a design under checking (DUC), and a self-checking circuit. The buffer is used to buffer data generated from a source device. The DUC is used to perform a designated function upon data read from the buffer when operating under a normal mode. The self-checking circuit is used to apply logic functional checking to the DUC when the DUC operates under a self-checking mode. When the DUC operates under the self-checking mode, the buffer keeps buffering data generated from the source device.

公开(公告)号：US10306246B2

公开(公告)日：2019-05-28

申请号：US15010062

申请日：2016-01-29

Applicant: MediaTek Inc.

Inventor： Ping Chao ,  Huei-Min Lin ,  Chih-Ming Wang ,  Yung-Chang Chang

IPC: H04N19/42 ,  H04N19/82 ,  H04N19/86

Abstract: A method and apparatus for loop filter processing of reconstructed video data for a video coding system are disclosed. The system receives reconstructed video data for an image unit. The loop filter processing is applied to reconstructed pixels above a deblocking boundary of the current CTU. In order to reduce line buffer requirement and/or to reduce loop filter switching for image units, the sample adaptive offset (SAO) parameter boundary and spatial-loop-filter restricted boundary for the luma and chroma components are determined by global consideration. In one embodiment, the SAO parameter boundary and the spatial-loop-filter restricted boundary are aligned for the luma and chroma components respectively. In another embodiment, the SAO parameter boundary and the spatial-loop-filter restricted boundary for the luma and chroma components are all aligned.

公开(公告)号：US20180329371A1

公开(公告)日：2018-11-15

申请号：US15974701

申请日：2018-05-09

Applicant: MEDIATEK INC.

Inventor： Huei-Min Lin ,  Yi-Chang Chen ,  Chih-Ming Wang ,  Yung-Chang Chang

IPC: G05B9/02 ,  G06F11/00 ,  G06F1/08 ,  G06F3/06

Abstract: A data processing system includes a buffer, a design under checking (DUC), and a self-checking circuit. The buffer is used to buffer data generated from a source device. The DUC is used to perform a designated function upon data read from the buffer when operating under a normal mode. The self-checking circuit is used to apply logic functional checking to the DUC when the DUC operates under a self-checking mode. When the DUC operates under the self-checking mode, the buffer keeps buffering data generated from the source device.