Soft FEC With Parity Check
    1.
    发明公开

    公开(公告)号:US20230327806A1

    公开(公告)日:2023-10-12

    申请号:US18210823

    申请日:2023-06-16

    IPC分类号: H04L1/00

    摘要: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.

    Soft FEC with parity check
    2.
    发明授权

    公开(公告)号:US11683124B2

    公开(公告)日:2023-06-20

    申请号:US17677481

    申请日:2022-02-22

    IPC分类号: H04L1/00

    摘要: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.

    METHODS AND SYSTEMS FOR DATA TRANSMISSION

    公开(公告)号:US20220158759A1

    公开(公告)日:2022-05-19

    申请号:US17592054

    申请日:2022-02-03

    摘要: An optical transmitter includes a first encoder, a first interleaver, a second encoder, a mapper, a second interleaver, and a frame generator. The first encoder is configured to encode data using a staircase code to generate first codewords. The first interleaver is configured to interleave the first codewords using convolutional interleaving to spread a transmission order of the first codewords. The second encoder is configured to encode the interleaved first codewords using a second code to generate second codewords. The mapper is configured to map the second codewords to transmit symbols. The second interleaver is configured to interleave the transmit symbols to distribute the transmit symbols between pilot symbols. The frame generator is configured to generate a transmit frame including the interleaved transmit symbols and the pilot symbols.

    Soft FEC with parity check
    4.
    发明授权

    公开(公告)号:US11277224B2

    公开(公告)日:2022-03-15

    申请号:US16928821

    申请日:2020-07-14

    IPC分类号: H04L1/00 H04B14/02 H03M13/29

    摘要: A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.

    Tracking of sampling phase in a receiver device

    公开(公告)号:US12120210B2

    公开(公告)日:2024-10-15

    申请号:US17993776

    申请日:2022-11-23

    IPC分类号: H04L7/00 H04L7/033

    CPC分类号: H04L7/0012 H04L7/033

    摘要: An input signal is sampled at a current sampling phase by a sampler device of a receiver device. The sampled input signal is equalized by an adaptive equalizer of the receiver device. One or more parameters of the adaptive equalizer are adapted, based on the equalized input signal, under one or more adaptation constraints. Phase gradient information indicative of an offset of the current sampling phase from an optimal sampling phase is determined, and the one or more adaptation constraints of the adaptive equalizer are updated based on the phase gradient information to move the current sampling phase towards the optimal sampling phase.

    Hybrid analog/digital equalizer architecture for high-speed receiver

    公开(公告)号:US11876649B2

    公开(公告)日:2024-01-16

    申请号:US17648440

    申请日:2022-01-20

    IPC分类号: H04L25/03 H04L25/02

    摘要: Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.

    Systems and methods for interleaved hamming encoding and decoding

    公开(公告)号:US11356122B2

    公开(公告)日:2022-06-07

    申请号:US16818864

    申请日:2020-03-13

    IPC分类号: H03M13/00 H03M13/27 H03M13/15

    摘要: A communication device includes a first alignment circuit configured to receive, from a host device, a first encoded data stream including a plurality of symbols encoded with a first type of error correction code. The first alignment circuit is configured to output an aligned first encoded data stream that is aligned to boundaries between the plurality of symbols encoded with the first type of error correction code. An interleaver is configured to interleave the plurality of symbols of the aligned first encoded data stream into symbol sections each including a predetermined number of symbols encoded with the first type of error correction code. An encoder is configured to generate, for each of the symbol sections, a parity block corresponding to the symbols in the symbol section and to output a second encoded data stream including the aligned first encoded data stream and the parity block.

    Soft FEC with parity check
    9.
    发明授权

    公开(公告)号:US11804925B2

    公开(公告)日:2023-10-31

    申请号:US17693931

    申请日:2022-03-14

    IPC分类号: H04L1/00 H03M13/15 H03M13/29

    摘要: A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.

    Soft FEC with parity check
    10.
    发明授权

    公开(公告)号:US11265109B2

    公开(公告)日:2022-03-01

    申请号:US16824261

    申请日:2020-03-19

    IPC分类号: H04L1/00

    摘要: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that processes an interleaved data stream and generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.