公开(公告)号：US11869831B2

公开(公告)日：2024-01-09

申请号：US17460352

申请日：2021-08-30

Applicant: MEDIATEK INC.

Inventor： Chin-Chiang Chang ,  Yin-Fa Chen ,  Shih-Chin Lin

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49541 ,  H01L23/3107 ,  H01L23/49503 ,  H01L24/48 ,  H01L2224/48175

Abstract: A semiconductor package includes a die attach pad, a plurality of lead terminals positioned about the die attach pad and disposed along side edges of the semiconductor package, a semiconductor die mounted on the die attach pad, a molding compound encapsulating the plurality of lead terminals and the semiconductor die, and at least one dummy lead disposed in a corner region of the semiconductor package between the plurality of lead terminals.

公开(公告)号：US20240006278A1

公开(公告)日：2024-01-04

申请号：US18200590

申请日：2023-05-23

Applicant: MEDIATEK INC.

Inventor： Hsin-Long Chen ,  Chin-Chiang Chang

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H10B80/00 ,  H01L23/00

CPC classification number: H01L23/49805 ,  H01L25/0657 ,  H01L23/3107 ,  H10B80/00 ,  H01L24/48 ,  H01L24/73 ,  H01L24/32 ,  H01L24/16 ,  H01L24/45 ,  H01L2924/1436 ,  H01L2224/32245 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48011 ,  H01L2224/13147 ,  H01L2924/1433

Abstract: A multi-die QFN hybrid package includes a carrier having flip-chip leads and wire-bonding leads. A first die and a second die are mounted on the flip-chip leads, respectively, in a flip-chip manner. The first die is spaced apart from the second die. A third die is stacked over the first die and the second die. The third die is electrically connected to the wire-bonding leads around the first die and the second die through bond wires. A mold cap encapsulates the first die, the second die, the third die, the bond wires, and partially encapsulates the carrier. The flip-chip leads and the wire-bonding leads are exposed from a bottom mold cap surface.

公开(公告)号：US12230562B2

公开(公告)日：2025-02-18

申请号：US17691056

申请日：2022-03-09

Applicant: MEDIATEK INC.

Inventor： Chin-Chiang Chang

IPC: H01L23/498 ,  H01L23/31

Abstract: A three-dimensional pad structure includes a substrate; a pad disposed on the substrate, wherein a perimeter of the pad is covered with a solder mask; and at least one conductive pillar protruding from a top surface of the pad.

公开(公告)号：US11264309B2

公开(公告)日：2022-03-01

申请号：US16868511

申请日：2020-05-06

Applicant: MEDIATEK INC.

Inventor： Chin-Chiang Chang

IPC: H01L23/495

Abstract: A semiconductor package includes at least one die attach pad of a leadframe, at least one semiconductor die mounted on the at least one die attach pad; and a plurality of lead terminals disposed around the at least one die attach pad and electrically connected to respective input/output (I/O) pads on the at least one semiconductor die through a plurality of bond wires. The plurality of lead terminals comprises first lead terminals, second lead terminals, and third lead terminals, which are arranged in triple row configuration along at least one side of the semiconductor package. Each of the first lead terminals, second lead terminals, and third lead terminals has an exposed base metal on a cut end thereof.

公开(公告)号：US10037936B2

公开(公告)日：2018-07-31

申请号：US15176163

申请日：2016-06-08

Applicant: MEDIATEK INC.

Inventor： Shiann-Tsong Tsai ,  Hsueh-Te Wang ,  Chin-Chiang Chang

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L23/49586 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3157 ,  H01L23/4952 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3862 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A semiconductor package includes a carrier substrate having a top surface, a semiconductor die mounted on the top surface, a plurality of bonding wires connecting the semiconductor die to the carrier substrate, an insulating material coated on the bonding wires, and a molding compound covering the top surface and encapsulating the semiconductor die, the plurality of bonding wires, and the insulating material.

公开(公告)号：US20220115303A1

公开(公告)日：2022-04-14

申请号：US17460352

申请日：2021-08-30

Applicant: MEDIATEK INC.

Inventor： Chin-Chiang Chang ,  Yin-Fa Chen ,  Shih-Chin Lin

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes a die attach pad, a plurality of lead terminals positioned about the die attach pad and disposed along side edges of the semiconductor package, a semiconductor die mounted on the die attach pad, a molding compound encapsulating the plurality of lead terminals and the semiconductor die, and at least one dummy lead disposed in a corner region of the semiconductor package between the plurality of lead terminals.

公开(公告)号：US20170125327A1

公开(公告)日：2017-05-04

申请号：US15176163

申请日：2016-06-08

Applicant: MEDIATEK INC.

Inventor： Shiann-Tsong Tsai ,  Hsueh-Te Wang ,  Chin-Chiang Chang

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/49586 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3157 ,  H01L23/4952 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3862 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A semiconductor package includes a carrier substrate having a top surface, a semiconductor die mounted on the top surface, a plurality of bonding wires connecting the semiconductor die to the carrier substrate, an insulating material coated on the bonding wires, and a molding compound covering the top surface and encapsulating the semiconductor die, the plurality of bonding wires, and the insulating material.

公开(公告)号：US20160043040A1

公开(公告)日：2016-02-11

申请号：US14686783

申请日：2015-04-15

Applicant: MEDIATEK INC.

Inventor： Chin-Chiang Chang ,  Tao Cheng

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49838 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides an integrated circuit (IC) package with stress releasing structure. The IC package comprises: a metal plane, a substrate, an IC chip, and an IC fill layer. The metal plane has at least one first etching line for separating the metal plane into a plurality of areas. The substrate is formed on metal layer. The IC chip is formed on the substrate, and the IC fill layer is formed around the IC chip. The at least one first etching line forms at least one half cut line in the metal plane and the substrate.

Abstract translation: 本发明提供一种具有应力释放结构的集成电路（IC）封装。 IC封装包括：金属平面，基板，IC芯片和IC填充层。 金属平面具有用于将金属平面分离成多个区域的至少一个第一蚀刻线。 衬底形成在金属层上。 IC芯片形成在基板上，IC填充层围绕IC芯片形成。 所述至少一个第一蚀刻线在所述金属平面和所述基板中形成至少一条半切割线。

公开(公告)号：US20220328394A1

公开(公告)日：2022-10-13

申请号：US17691056

申请日：2022-03-09

Applicant: MEDIATEK INC.

Inventor： Chin-Chiang Chang

IPC: H01L23/498

Abstract: A three-dimensional pad structure includes a substrate; a pad disposed on the substrate, wherein a perimeter of the pad is covered with a solder mask; and at least one conductive pillar protruding from a top surface of the pad.

公开(公告)号：US09905515B2

公开(公告)日：2018-02-27

申请号：US14686783

申请日：2015-04-15

Applicant: MEDIATEK INC.

Inventor： Chin-Chiang Chang ,  Tao Cheng

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49838 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides an integrated circuit (IC) package with stress releasing structure. The IC package comprises: a metal plane, a substrate, an IC chip, and an IC fill layer. The metal plane has at least one first etching line for separating the metal plane into a plurality of areas. The substrate is formed on metal layer. The IC chip is formed on the substrate, and the IC fill layer is formed around the IC chip. The at least one first etching line forms at least one half cut line in the metal plane and the substrate.