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1.发明公开公开(公告)号：US20230289585A1
公开(公告)日：2023-09-14
申请号：US18319570
申请日：2023-05-18
发明人： Tayfun Gokmen , Seyoung Kim , Dennis M. Newns , Yurii A. Vlasov
IPC分类号： G06N3/065
摘要： A resistive processing unit (RPU) that includes a pair of transistors connected in series providing an update function for a weight of a training methodology to the RPU, and a read transistor for reading the weight of the training methodology. In some embodiments, the resistive processing unit (RPU) further includes a capacitor connecting a gate of the read transistor to the air of transistors providing the update function for the resistive processing unit (RPU). The capacitor stores said weight of training methodology for the RPU.
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公开(公告)号：US20220359617A1
公开(公告)日：2022-11-10
申请号：US17308499
申请日：2021-05-05
发明人： Seonghoon Woo , Seyoung Kim , Mingu Kang
摘要： A resistive memory device includes a magnetic tunnel junction structure. The magnetic tunnel junction structure includes a free magnetic layer. The free magnetic layer includes a magnetic material configurable to host topological spin textures to tune a conductance state of the resistive memory device.
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公开(公告)号：US20220188628A1
公开(公告)日：2022-06-16
申请号：US17121930
申请日：2020-12-15
发明人： Malte Johannes Rasch , Tayfun Gokmen , Seyoung Kim
摘要： A device which comprises an array of resistive processing unit (RPU) cells, first control lines extending in a first direction across the array of RPU cells, and second control lines extending in a second direction across the array of RPU cells. Peripheral circuitry comprising readout circuitry is coupled to the first and second control lines. A control system generates control signals to control the peripheral circuitry to perform a first operation and a second operation on the array of RPU cells. The control signals include a first configuration control signal to configure the readout circuitry to have a first hardware configuration when the first operation is performed on the array of RPU cells, and a second configuration control signal to configure the readout circuitry to have a second hardware configuration, which is different from the first hardware configuration, when the second operation is performed on the array of RPU cells.
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4.发明授权公开(公告)号：US11314483B2
公开(公告)日：2022-04-26
申请号：US16737440
申请日：2020-01-08
发明人： Mingu Kang , Seyoung Kim , Kyu-hyoun Kim , Eun Kyung Lee
摘要： A system is provided for error resiliency in a bit serial computation. A delay monitor enforces an overall processing duration threshold for bit-serial processing all iterations for the bit serial computation, while determining a threshold for processing each iteration. At least some iterations correspond to a respective bit in an input bit sequence. A clock generator generates a clock signal for controlling a performance of the iterations. Each of iteration units perform a particular iteration, starting with a Most Significant Bit (MSB) of the input bit sequence and continuing in descending bit significant order, and by selectively increasing the threshold for at least one iteration while skipping from processing at least one subsequent iteration whose iteration-level processing duration exceeds a remaining amount of an overall processing duration for all iterations, responsive to the at least one iteration requiring more time to complete than a current value of the threshold.
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公开(公告)号：US11301211B2
公开(公告)日：2022-04-12
申请号：US16847505
申请日：2020-04-13
发明人： Seyoung Kim , Mingu Kang , Kyu-hyoun Kim , Seonghoon Woo
摘要： A differential mixed-signal logic processor is provided. The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B. Each of the plurality of mixed-signal multiplier branches include a first capacitor connected across a second capacitor and a third capacitor to provide a differential output across the second and third capacitors. A capacitance of the first capacitor is equal to half a capacitance of the second and third capacitors.
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公开(公告)号：US11200297B2
公开(公告)日：2021-12-14
申请号：US16439246
申请日：2019-06-12
发明人： Seyoung Kim , Tayfun Gokmen , Malte Rasch
摘要： An apparatus and method are provided for saturation prevention of a current integrator in a Resistive Processing Unit-based (RPU-based) accelerator. The apparatus includes a set of hardware switches. The apparatus further includes a voltage generator, operatively coupled between an input terminal and an output terminal of the current integrator, reducing a magnitude of an output voltage at the output terminal of the current integrator during a current integration operation by selectively applying a non-zero initial voltage to the current integrator prior to the current integration operation, responsive to an operating state of the set of hardware switches.
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公开(公告)号：US11188826B2
公开(公告)日：2021-11-30
申请号：US16423398
申请日：2019-05-28
发明人： Tayfun Gokmen , Seyoung Kim
摘要： In some aspects, a method may include initializing a first array and a second array with a random voltage value, passing a forward pass by pulsing an input voltage value from an input of the first array and an input of the second array, and reading output voltage values at an output of the first array and an output of the second array. The method may further include passing a backward pass into the inputs of both of the first and second arrays, and reading voltage values at the inputs of the first and second arrays. The method may further include updating, with the first array, a first matrix update on the first array, updating, with the second array, a first matrix update on the second, and updating, with the second array, a second matrix update on the second array.
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8.发明授权公开(公告)号：US11157810B2
公开(公告)日：2021-10-26
申请号：US15954170
申请日：2018-04-16
发明人： Seyoung Kim , Tayfun Gokmen
摘要： Systems and methods are provided to perform weight update operations in a resistive processing unit (RPU) system to update weight values of RPU devices comprising tunable resistive device. A weight update operation for a given RPU device includes maintaining a weight update accumulation value for the RPU device, adjusting the weight update accumulation value by one unit update value in response to a detected coincidence of stochastic bits streams of input vectors applied on an update row and update column control lines connected to the RPU device, generating a weight update control signal in response to the accumulated weight value reaching a predefined threshold value, and adjusting a conductance level of the tunable resistive device by one unit conductance value in response to the weight update control signal, wherein the one unit conductance value corresponds to one unit weight value of the RPU device.
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公开(公告)号：US11055610B2
公开(公告)日：2021-07-06
申请号：US15639255
申请日：2017-06-30
发明人： Yulong Li , Paul Solomon , Effendi Leobandung , Chun-Chen Yeh , Seyoung Kim
摘要： A CMOS-based resistive processing unit (RPU) for a neural network. The RPU includes a capacitor device configured to store a charge representing a weight value associated with a neural network circuit operation. A current source Field Effect Transistor (FET) device is operatively connected to the capacitor device for increasing a charge on the capacitor. A current sink FET device operatively connected to the capacitor device is configured for decreasing the stored capacitor charge. An analog weight update circuit receives one or more update signals generated in conjunction with the neural network circuit operation, the analog weight update circuit controlling the current source FET device and the current sink FET device to provide either a determined amount of current to increase the stored charge on the capacitor device, or sink a determined amount of current to decrease the stored charge on the capacitor device.
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公开(公告)号：US10833268B2
公开(公告)日：2020-11-10
申请号：US16287485
申请日：2019-02-27
发明人： Hiroyuki Miyazoe , Takashi Ando , Asit Ray , Seyoung Kim
摘要： Devices and/or methods that facilitate forming a resistive memory crossbar array with a multilayer hardmask are provided. In some embodiments, a resistive random access memory (RRAM) can comprise a multilayer hardmask comprising three layers, an interlayer oxide between a first layer of silicon nitride and a second layer of silicon nitride. In other embodiments, an RRAM can comprise a multilayer hardmask comprising two layers, a layer of an oxide on a layer of silicon nitride.
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