公开(公告)号：US20240313069A1

公开(公告)日：2024-09-19

申请号：US18676612

申请日：2024-05-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Lingcong LE ,  Zheng ZHONG ,  Haijun LI ,  Huilan HU ,  Ping MA

IPC: H01L29/40 ,  H01L23/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/778

CPC classification number: H01L29/404 ,  H01L23/66 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7786 ,  H01L2223/6677

Abstract: A semiconductor component and an electronic device are structured to reduce a gate-drain parasitic capacitance of the semiconductor component. The semiconductor component includes: a substrate; a channel layer and a barrier layer that are sequentially stacked on the substrate; a source and a drain that are disposed on the barrier layer; a first gate and a second gate that are disposed on the barrier layer. The first gate and the second gate are located between the source and the drain, and the second gate is disposed between the first gate and the drain. A first gate field plate is at least partially disposed on a side that is of the first gate and that is close to the drain; and a first source field plate. The first source field plate covers the first gate field plate.

公开(公告)号：US20230299022A1

公开(公告)日：2023-09-21

申请号：US18324071

申请日：2023-05-25

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Cen TANG ,  Jin RAO ,  Tao LIU ,  Haijun LI ,  Wei LU ,  Lingcong LE ,  Juncai MA ,  Zhili ZHANG

IPC: H01L23/66 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L23/66 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/402

Abstract: A semiconductor device includes a substrate, a gate, a second dielectric layer, and a field plate. The substrate has a first dielectric layer, and a thickness of the first dielectric layer in a first area is greater than a thickness of the first dielectric layer in a second area outside the first area. The gate is located on the substrate and in the first area, the gate includes a first gate structure and a second gate structure, and the second gate structure is formed on a side of the first dielectric layer that is away from the substrate and covers a part of the first dielectric layer. The second dielectric layer covers the gate and the first dielectric layer. The field plate is located on the second dielectric layer and is disposed in both the first area and the second area.

公开(公告)号：US20240274688A1

公开(公告)日：2024-08-15

申请号：US18603994

申请日：2024-03-13

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Zhili ZHANG ,  Jin RAO ,  Tao LIU ,  Haijun LI ,  Shuiming LI ,  Ming LU

IPC: H01L29/45 ,  H01L21/285 ,  H01L21/768 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778 ,  H03F3/213

CPC classification number: H01L29/452 ,  H01L21/28575 ,  H01L21/76898 ,  H01L23/3675 ,  H01L23/3735 ,  H01L23/481 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/7786 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48175 ,  H01L2224/73265 ,  H01L2924/1033 ,  H01L2924/13064 ,  H01L2924/1421 ,  H03F3/213

Abstract: The present disclosure relates to semiconductor devices, manufacturing methods, a power amplification circuits, and electronic devices. One example semiconductor device includes a substrate, a channel layer and a barrier layer sequentially disposed on the substrate in a stacked manner, a source, a gate, and a drain disposed on the barrier layer, a backside via through a region from the substrate to the barrier layer below the source, and a backside conductive layer covering the backside via and a back surface of the substrate, where the source is in contact with and connected to the backside conductive layer.

公开(公告)号：US20230398894A1

公开(公告)日：2023-12-14

申请号：US18237514

申请日：2023-08-24

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Haijun LI ,  Zhen FAN

IPC: B60L53/62 ,  B60L53/30 ,  B60L53/14

CPC classification number: B60L53/62 ,  B60L53/305 ,  B60L53/14

Abstract: This application discloses a charging control apparatus and method, and an electric vehicle. The charging control apparatus includes: a signal processing module, configured to: receive a first control pilot signal sent by power sourcing equipment, and send a high-level signal of target duration to a wake-up module based on the first control pilot signal; and the wake-up module, configured to: wake up a battery management system after duration in which the high-level signal is received reaches the target duration. With the use of the charging control apparatus, even if power is on again after a power failure in a charging process, there is no need to remove a charging connector from and re-insert the charging connector into a charging socket or restart an electric vehicle/a charging pile.

公开(公告)号：US20230395455A1

公开(公告)日：2023-12-07

申请号：US18454876

申请日：2023-08-24

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Shuiming LI ,  Yu WANG ,  Ping MA ,  Ming LU ,  Cen TANG ,  Zhili ZHANG ,  Qiang HE ,  Haijun LI ,  Tao LIU ,  Jin RAO

IPC: H01L23/367 ,  H01L23/373 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L23/367 ,  H01L23/3735 ,  H01L23/3736 ,  H01L29/66462 ,  H01L29/7786

Abstract: Embodiments of this application provide a semiconductor device, an electronic device, and a semiconductor device preparation method, and relate to the field of chip manufacturing and packaging technologies, to improve heat dissipation efficiency of the semiconductor device without increasing a size. The semiconductor device includes: a substrate, a source, a drain, a gate, and a groove. The source, the drain, and the gate are all formed on the substrate, and an active region is formed between the source and the drain on the substrate. The groove is disposed in the substrate, and a spacing is formed between the groove and the active region. A heat dissipation layer is formed in the groove, and a coefficient of thermal conductivity of the heat dissipation layer is greater than that of the substrate.

公开(公告)号：US20230343835A1

公开(公告)日：2023-10-26

申请号：US18334541

申请日：2023-06-14

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Zhili ZHANG ,  Jin RAO ,  Tao LIU ,  Haijun LI ,  Wei LU ,  Shuiming LI ,  Cen TANG ,  Qiang HE ,  Juncai MA ,  Chunhua FAN ,  Yangyi ZHU

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66

CPC classification number: H01L29/402 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/401 ,  H01L29/66462

Abstract: The technology of this application relates to a high electron mobility transistor including a GaN substrate layer, a barrier layer, a circuit layer, and a field plate that are sequentially stacked. The GaN substrate layer includes a main body layer and a channel layer that are stacked, the channel layer is adjacent to the barrier layer, the circuit layer includes a source, a drain, and a dielectric layer, the dielectric layer is disposed between the source and the drain, the field plate is disposed on a side that is of the dielectric layer and that is away from the barrier layer, an orthographic projection of the field plate on the channel layer is a field plate projection, the channel layer includes a modulation region and a non-modulation region, the non-modulation region surrounds the modulation region, the modulation region and the field plate projection at least partially overlap.