公开(公告)号：US20180040362A1

公开(公告)日：2018-02-08

申请号：US15604406

申请日：2017-05-24

申请人： Dong-Hun KWAK ,  Hee-Woong KANG ,  Jun-Ho SEO ,  Hee-Won LEE

发明人： Dong-Hun KWAK ,  Hee-Woong KANG ,  Jun-Ho SEO ,  Hee-Won LEE

IPC分类号： G11C11/4074 ,  G11C16/30 ,  G11C16/06 ,  G11C11/408 ,  G11C16/34 ,  G11C11/56 ,  G11C11/4097 ,  G11C16/04 ,  G11C16/10

CPC分类号： G11C11/4074 ,  G11C7/109 ,  G11C7/12 ,  G11C8/12 ,  G11C11/4082 ,  G11C11/4085 ,  G11C11/4097 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3436 ,  G11C2207/2209

摘要： A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.