公开(公告)号：US10062602B2

公开(公告)日：2018-08-28

申请号：US14142124

申请日：2013-12-27

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  CNRS Centre National de la Recherche Scientifique ,  APPLIED MATERIALS, Inc.

Inventor： Nicolas Posseme ,  Sebastien Barnola ,  Olivier Joubert ,  Srinivas Nemani ,  Laurent Vallier

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76802 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76814 ,  H01L2221/1063

Abstract: The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at least one silicon-based gas mixed with oxygen (O2) and/or nitrogen (N2) so as to grow a passivation layer all along said etching, at least on flanks of the layer of porous dielectric material and wherein the silicon-based gas is taken from all the compounds of the type SixHy for which the ratio x/y is equal or greater than 0.3 or is taken from all the compounds of the following types: SixFy and SixCly, where x is the proportion of silicon (Si) in the gas and y is the proportion of fluorine (F) or chlorine (Cl) or hydrogen (H) in the gas.

公开(公告)号：US20160300709A1

公开(公告)日：2016-10-13

申请号：US15091916

申请日：2016-04-06

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  CNRS Centre National de la Recherche Scientifique ,  APPLIED MATERIALS, Inc.

Inventor： Nicolas POSSEME ,  Thibaut David ,  Olivier Joubert ,  Thorsten Lill ,  Srinivas Nemani ,  Laurent Vallier

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/306

CPC classification number: H01L21/0234 ,  H01L21/0217 ,  H01L21/02321 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L29/66628 ,  H01L29/66772

Abstract: A method is provided for forming spacers for a gate of a field effect transistor, the gate being situated above a layer of semiconductor material, including forming a layer of nitride covering the gate; modifying the layer by plasma implantation of light ions, having an atomic number equal or less than 10, in the layer in order to form a modified layer of nitride, the modifying being performed so as not to modify the layer of nitride over its entire thickness at flanks of the gate; and removing the modified layer of nitride by a selective wet or dry etching, of the modified layer relative to said layer of semiconductor material and relative to the non-modified layer at the flanks of the gate, without etching the layer of semiconductor material, wherein an entire length of the non-modified layer at the flanks remains after the selective wet or dry etching.

Abstract translation: 提供一种用于形成场效应晶体管的栅极的间隔物的方法，栅极位于半导体材料层之上，包括形成覆盖栅极的氮化物层; 通过在层中等离子体注入原子数等于或小于10的光离子来修饰层，以便形成改性的氮化物层，进行修饰以在其整个厚度上不改变氮化物层 在门的侧面; 以及通过选择性湿法或干法蚀刻，相对于所述半导体材料层和相对于栅极侧面处的非改性层，相对于未改性层，通过选择性湿法或干蚀刻去除修饰的氮化物层，而不蚀刻半导体材料层，其中 在选择性湿法或干蚀刻之后，侧面上未改性层的整个长度保留。

公开(公告)号：US08956886B2

公开(公告)日：2015-02-17

申请号：US14204668

申请日：2014-03-11

Applicant: Applied Materials, Inc.

Inventor： Samer Banna ,  Olivier Joubert ,  Lei Lian ,  Maxime Darnon ,  Nicolas Posseme ,  Laurent Vallier

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/311 ,  H01L21/027 ,  H01L21/67 ,  H01L21/308 ,  H01L21/3213 ,  G03F7/20

CPC classification number: H01L22/26 ,  G03F7/70625 ,  H01L21/0273 ,  H01L21/3086 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/67253 ,  H01L22/12 ,  H01L22/20

Abstract: In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.

Abstract translation: 在一些实施例中，在半导体制造工艺中控制光致抗蚀剂修剪工艺的方法可以包括在衬底的第一表面之上形成光致抗蚀剂层，其中光致抗蚀剂层包括具有要蚀刻到第一表面中的第一图案的下层 以及具有未蚀刻到所述基板的第一表面中的第二图案的上层; 在平行于基板的第一表面的方向上修整光致抗蚀剂层; 在修整过程中使用光学测量工具测量第二图案的修剪率; 以及将所述第二图案的修整率与所述第一图案的修剪率相关联，以在所述修整处理期间控制所述第一图案的修整率。

公开(公告)号：US09583339B2

公开(公告)日：2017-02-28

申请号：US15091916

申请日：2016-04-06

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  CNRS Centre National de la Recherche Scientifique ,  APPLIED MATERIALS, Inc.

Inventor： Nicolas Posseme ,  Thibaut David ,  Olivier Joubert ,  Thorsten Lill ,  Srinivas Nemani ,  Laurent Vallier

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/306 ,  H01L21/265 ,  H01L21/3065

CPC classification number: H01L21/0234 ,  H01L21/0217 ,  H01L21/02321 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L29/66628 ,  H01L29/66772

Abstract: A method is provided for forming spacers for a gate of a field effect transistor, the gate being situated above a layer of semiconductor material, including forming a layer of nitride covering the gate; modifying the layer by plasma implantation of light ions, having an atomic number equal or less than 10, in the layer in order to form a modified layer of nitride, the modifying being performed so as not to modify the layer of nitride over its entire thickness at flanks of the gate; and removing the modified layer of nitride by a selective wet or dry etching, of the modified layer relative to said layer of semiconductor material and relative to the non-modified layer at the flanks of the gate, without etching the layer of semiconductor material, wherein an entire length of the non-modified layer at the flanks remains after the selective wet or dry etching.

Abstract translation: 提供一种用于形成场效应晶体管的栅极的间隔物的方法，栅极位于半导体材料层之上，包括形成覆盖栅极的氮化物层; 通过在层中等离子体注入原子数等于或小于10的光离子来修饰层，以便形成改性的氮化物层，进行修饰以在其整个厚度上不改变氮化物层 在门的侧面; 以及通过选择性湿法或干法蚀刻，相对于所述半导体材料层和相对于栅极侧面处的非改性层，相对于未改性层，通过选择性湿法或干蚀刻去除修饰的氮化物层，而不蚀刻半导体材料层，其中 在选择性湿法或干蚀刻之后，侧面上未改性层的整个长度保留。