Invention Grant
- Patent Title: Embedded test structure for trimming process control
- Patent Title (中): 用于修整过程控制的嵌入式测试结构
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Application No.: US14204668Application Date: 2014-03-11
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Publication No.: US08956886B2Publication Date: 2015-02-17
- Inventor: Samer Banna , Olivier Joubert , Lei Lian , Maxime Darnon , Nicolas Posseme , Laurent Vallier
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Moser Taboada
- Agent Alan Taboada
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/66 ; H01L21/311 ; H01L21/027 ; H01L21/67 ; H01L21/308 ; H01L21/3213 ; G03F7/20

Abstract:
In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.
Public/Granted literature
- US20140273297A1 EMBEDDED TEST STRUCTURE FOR TRIMMING PROCESS CONTROL Public/Granted day:2014-09-18
Information query
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