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    Configurable clock grid structures
    2.
    发明授权
    Configurable clock grid structures 有权

    公开(公告)号：US09606573B1

    公开(公告)日：2017-03-28

    申请号：US14752393

    申请日：2015-06-26

    Applicant: Altera Corporation

    Inventor： Carl Ebeling ,  Dana How ,  Herman Henry Schmit ,  Vadim Gutnik ,  Ramanand Venkata

    IPC: H03K3/00 ,  G06F1/08

    CPC classification number: G06F1/08 ,  G06F1/10

    Abstract: Circuitry accepts an input signal and distributes the input signal to a plurality of locations within the circuitry. The circuitry includes a first circuit element and a second circuit element. The circuitry further includes a first plurality of wire segments that are substantially aligned to form a first bundle, and include a first wire segment. The circuitry further includes a second plurality of wire segments that are substantially aligned to form a second bundle, and have a second wire segment. An intersection element of the first bundle and the second bundle includes a first interconnecting wire segment that connects the first wire segment and the second wire segment, and the input signal is routed from the first wire segment to the second wire segment via the first interconnecting wire segment. The input signal is further transmitted to the second element from the second wire segment.

    Techniques for providing clock signals in an integrated circuit
    4.
    发明授权
    Techniques for providing clock signals in an integrated circuit 有权
    在集成电路中提供时钟信号的技术

    公开(公告)号：US09024673B1

    公开(公告)日：2015-05-05

    申请号：US14075869

    申请日：2013-11-08

    Applicant: Altera Corporation

    Inventor： Ramanand Venkata ,  Ryan Fung ,  Ketan H. Zaveri

    IPC: G06F1/04 ,  G06F1/10

    CPC classification number: G06F1/10

    Abstract: An integrated circuit includes a first vertical clock bus and a first interface circuit coupled to provide first global clock signals to the first vertical clock bus. The first interface circuit is coupled to a first external terminal of the integrated circuit. The integrated circuit also includes a second vertical clock bus and a second interface circuit coupled to provide second global clock signals to the second vertical clock bus. The second interface circuit is coupled to a second external terminal of the integrated circuit. A third horizontal clock bus is coupled to provide the first and the second global clock signals from the first and the second vertical clock buses to a center region of the integrated circuit.

    Abstract translation: 集成电路包括第一垂直时钟总线和耦合以向第一垂直时钟总线提供第一全局时钟信号的第一接口电路。 第一接口电路耦合到集成电路的第一外部端子。 集成电路还包括第二垂直时钟总线和耦合以向第二垂直时钟总线提供第二全局时钟信号的第二接口电路。 第二接口电路耦合到集成电路的第二外部端子。 第三水平时钟总线被耦合以将第一和第二全局时钟信号从第一和第二垂直时钟总线提供给集成电路的中心区域。

    CONFIGURATION VIA HIGH SPEED SERIAL LINK
    5.
    发明申请
    CONFIGURATION VIA HIGH SPEED SERIAL LINK 有权

    公开(公告)号：US20210011875A1

    公开(公告)日：2021-01-14

    申请号：US16872246

    申请日：2020-05-11

    Applicant: Altera Corporation

    Inventor： Ramanand Venkata ,  Gopi Krishnamurthy

    IPC: G06F13/40 ,  G06F13/42

    Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

    SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PROGRAMMABLE LOGIC DEVICE INTEGRATED CIRCUITS
    9.
    发明申请
    SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PROGRAMMABLE LOGIC DEVICE INTEGRATED CIRCUITS 审中-公开
    用于可编程逻辑器件集成电路的高速串行数据传输器的串行电路

    公开(公告)号：US20140009188A1

    公开(公告)日：2014-01-09

    申请号：US14022639

    申请日：2013-09-10

    Applicant: Altera Corporation

    Inventor： Toan Thanh Nguyen ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong H. Lee

    IPC: H03K19/00

    CPC classification number: H03K19/00 ,  H03K19/17744 ,  H03M9/00 ,  H04L1/243 ,  H04L7/0008 ,  H04L7/033 ,  H04L25/0266

    Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

    Abstract translation: 用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。 电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

    DIGITAL PHASE LOCKED LOOP CIRCUITRY AND METHODS
    10.
    发明申请
    DIGITAL PHASE LOCKED LOOP CIRCUITRY AND METHODS 有权
    数字相位锁定环路和方法

    公开(公告)号：US20130265179A1

    公开(公告)日：2013-10-10

    申请号：US13907158

    申请日：2013-05-31

    Applicant: Altera Corporation

    Inventor： Ramanand Venkata ,  Chong H. Lee

    IPC: H03M9/00

    CPC classification number: H03M9/00 ,  H03L7/089 ,  H03L2207/50 ,  H04L7/0008 ,  H04L7/0337

    Abstract: Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

    Abstract translation: 锁相环电路以数字方式进行数字操作，至少在很大程度上从多个相位分布的候选时钟信号中选择最接近相位的信号，以便在诸如时钟数据恢复（“CDR”）信号的另一个信号中转换 。 该电路被构造和操作以避免由于候选时钟信号的选择变化而导致的输出时钟信号中的毛刺。 候选时钟信号的分频可以用于帮助电路以低于锁相环电路的模拟部分可以经济地提供的频率的比特率来支持串行通信。 出于同样的原因，发射侧可能会使用过量传输或过采样。

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