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公开(公告)号：US11221203B1
公开(公告)日：2022-01-11
申请号：US17009072
申请日：2020-09-01
Applicant: Allegro MicroSystems, LLC
Inventor： Florencia Ferrer , Jesse Lapomardo , Lautaro Casella , Lucas Intile
Abstract: In one aspect, a magnetic field sensor includes a magnetic field sensing element configured to detect changes in a magnetic field caused by a target and an encoder configured to process signals originating from the magnetic field element. The encoder is configured to generate a first output signal and a second output signal. In a non-fault state, the first and second output signals are 90 electrical degrees out of phase from one another, and in a fault state, the first and second output signals are in phase with each other.
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公开(公告)号：US11811569B2
公开(公告)日：2023-11-07
申请号：US17009111
申请日：2020-09-01
Applicant: Allegro MicroSystems, LLC
Inventor： Florencia Ferrer , Jesse Lapomardo , Lucas Intile
CPC classification number: H04L27/18 , G06F16/2365
Abstract: A sensor includes a sensing element to produce a sensing element signal and a processor responsive to the sensing element signal to generate a sensor output signal comprising a Single Edge Nibble Transmission (SENT) frame. The SENT frame includes a Status and Communication (SCN) nibble comprising a bit 0 and a bit 1 that represent a status of at least one internal diagnostic indicator and a plurality of data nibbles. At least one of the plurality of data nibbles includes a cyclic redundancy check (CRC), the CRC being an encoding of the bit 0 and the bit 1 of the SCN nibble and the plurality of data nibbles and at least one of the plurality of data nibbles includes a count that indicates a new frame, the CRC being at least a five bit value.
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公开(公告)号：US20220070035A1
公开(公告)日：2022-03-03
申请号：US17009111
申请日：2020-09-01
Applicant: Allegro MicroSystems, LLC
Inventor： Florencia Ferrer , Jesse Lapomardo , Lucas Intile
Abstract: A sensor includes a sensing element to produce a sensing element signal and a processor responsive to the sensing element signal to generate a sensor output signal comprising a Single Edge Nibble Transmission (SENT) frame. The SENT frame includes a Status and Communication (SCN) nibble comprising a bit 0 and a bit 1 that represent a status of at least one internal diagnostic indicator and a plurality of data nibbles. At least one of the plurality of data nibbles includes a cyclic redundancy check (CRC), the CRC being an encoding of the bit 0 and the bit 1 of the SCN nibble and the plurality of data nibbles and at least one of the plurality of data nibbles includes a count that indicates a new frame, the CRC being at least a five bit value.
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公开(公告)号：US11128282B2
公开(公告)日：2021-09-21
申请号：US16780324
申请日：2020-02-03
Applicant: Allegro MicroSystems, LLC
Inventor： Sergio Nicolás Deligiannis , Lucas Intile , Florencia Ferrer
IPC: H03K3/0233 , G01R31/3185 , H03K3/00 , H03K17/22 , H03K17/20 , G06F1/24 , H03K3/037
Abstract: A system is provided, comprising: a plurality of flip-flops that are configured to receive a reset signal, each of the plurality of flip-flops having a respective output port, and each of the plurality of flip-flops being configured to assume a respective default state when the reset signal is set to a predetermined value; and a reset monitor circuit that is coupled to the respective output port of each of the plurality of flip-flops, the reset monitor circuit being configured to generate a status signal indicating whether each of the flip-flops has assumed the flip-flop's respective default state after the reset signal is set to the predetermined value, wherein assuming a respective default state by each of the plurality of flip-flops results in a predetermined bit string being stored in the plurality of flip-flops.
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公开(公告)号：US20210239758A1
公开(公告)日：2021-08-05
申请号：US16780324
申请日：2020-02-03
Applicant: Allegro MicroSystems, LLC
Inventor： Sergio Nicolás Deligiannis , Lucas Intile , Florencia Ferrer
IPC: G01R31/3185
Abstract: A system is provided, comprising: a plurality of flip-flops that are configured to receive a reset signal, each of the plurality of flip-flops having a respective output port, and each of the plurality of flip-flops being configured to assume a respective default state when the reset signal is set to a predetermined value; and a reset monitor circuit that is coupled to the respective output port of each of the plurality of flip-flops, the reset monitor circuit being configured to generate a status signal indicating whether each of the flip-flops has assumed the flip-flop's respective default state after the reset signal is set to the predetermined value, wherein assuming a respective default state by each of the plurality of flip-flops results in a predetermined bit string being stored in the plurality of flip-flops.
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Patent Agency Ranking
公开(公告)号：US20240195424A1
公开(公告)日：2024-06-13
申请号：US18063809
申请日：2022-12-09
Applicant: Allegro MicroSystems, LLC
Inventor： Florencia Ferrer , Lucas Intile , Juan Manuel Cesaretti , Nicolás Rigoni
CPC classification number: H03L7/0991 , H03D13/001 , H03K3/12
Abstract: Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.
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公开(公告)号：US20210157669A1
公开(公告)日：2021-05-27
申请号：US16695968
申请日：2019-11-26
Applicant: Allegro MicroSystems, LLC
Inventor： Nicolas Rigoni , Fernando Orge , Lucas Intile , Nicolás Rafael Biberidis , Leandro Tozzi
Abstract: In one aspect, an integrated circuit (IC) includes a multiplexor configured to receive data from a non-volatile memory and configured to receive data from a shadow memory, a shift register configured to generate a first signature from the data received from the non-volatile memory and configured to generate a second signature from the data received from the shadow memory; a signature storage configured to store the first signature; and a shadow memory checking controller configured to enable the multiplexor to send the data from the non-volatile memory to the shift register, and send a command to reload the shadow memory with data from the non-volatile memory in response to receiving an error flag. The IC also includes a comparator circuit configured to compare the first signature and the second signature and configured to send the error flag in response to the first signature and the second signature being different.
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公开(公告)号：US20240364353A1
公开(公告)日：2024-10-31
申请号：US18768179
申请日：2024-07-10
Applicant: Allegro MicroSystems, LLC
Inventor： Florencia Ferrer , Lucas Intile , Juan Manuel Cesaretti , Nicolás Rigoni
CPC classification number: H03L7/0991 , H03D13/001 , H03K3/12
Abstract: Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.
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公开(公告)号：US12063046B2
公开(公告)日：2024-08-13
申请号：US18063809
申请日：2022-12-09
Applicant: Allegro MicroSystems, LLC
Inventor： Florencia Ferrer , Lucas Intile , Juan Manuel Cesaretti , Nicolás Rigoni
CPC classification number: H03L7/0991 , H03D13/001 , H03K3/12
Abstract: Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.
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公开(公告)号：US11055165B2
公开(公告)日：2021-07-06
申请号：US16695968
申请日：2019-11-26
Applicant: Allegro MicroSystems, LLC
Inventor： Nicolas Rigoni , Fernando Orge , Lucas Intile , Nicolás Rafael Biberidis , Leandro Tozzi
Abstract: In one aspect, an integrated circuit (IC) includes a multiplexor configured to receive data from a non-volatile memory and configured to receive data from a shadow memory, a shift register configured to generate a first signature from the data received from the non-volatile memory and configured to generate a second signature from the data received from the shadow memory; a signature storage configured to store the first signature; and a shadow memory checking controller configured to enable the multiplexor to send the data from the non-volatile memory to the shift register, and send a command to reload the shadow memory with data from the non-volatile memory in response to receiving an error flag. The IC also includes a comparator circuit configured to compare the first signature and the second signature and configured to send the error flag in response to the first signature and the second signature being different.
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